By Marek Perkowski

Portland State University
College of Engineering and Computer Science
ECE 573 Design of Sequential Circuits.
Course Schedule, Winter 2007
Updated March 3, 2009

Important Information:
  1. This class no longer needs the ECE 572 as a prerequisite. Some small material based on ECE 572 will be reviewed.
  2. The Friday meetings are recommended but not mandatory. I will always announce what will be covered on each Friday.
  3. There are two grading options: "homework/exam" and "project". The second option is recommended to anybody who is interested in writing thesis and publishing in journals as well as those that have interest in practical software implementation of the algorithms and methods introduced in the class.
  4. In the "homework/exam" option the grade is based on homeworks, exams (2 midterms) and project. Project is 40% of grade.
  5. In the "project only" option the grade is based entirely on the project.
  6. Students who take the "project only option" may still take midterms and solve homeworks to check their knowledge of material. This may improve their grade but is not mandatory.

    This is a list of lectures that will be taught in Spring 2009. If the student selects "homework/exam" grading all of them are required for exams.


    Lecture 1: What is this class about and review of sequential circuits.
    1. Class contents:
      synchronous and asynchronous circuits and automata: minimization, encoding, decomposition, synthesis.
      Cellular Automata and applications.
      Test and verification of automata.
      Timing and retiming.
      Design of circuits and systems for image processing, DSP and robotics.
    2. Shift register. Generalized register. Role of multiplexers. Analysis of shift registers. State graphs and state tables.
    3. Mealy, Moore, Rabin-Scott and Autonomous State Machines.
    4. Cellular Automata - one and two dimensional.
    5. Example of data flow description - sorting circuit: realization as pipelined, realization as combinational butterfly, realization as sequential controller.
    6. Generalizations of sorter: sorter-absorber, sorter of 2D cubes, sorter for symmetric functions.
    Lecture 2. Finite State Machines and their minimization.
      Mandatory Slides

    1. Review of Finite State Machines. Notation for machines. Mealy machine tables and graphs. Moore machine description. Practical problem to solve. Flip-Flops overview.
    2. Introduction to Minimization of Finite State Machines. Completely Specified Machines. The problem of state minimization. Algorithms and complexity. Minimization using state graphs. Complete vs incomplete machines. Partition-based minimization of complete machines in Kiss Format. Method of successive partitions. Implication chart method. Minimizing incompletely specified machines.

What will be discussed on Friday?
  1. Shift registers. Mealy, Moore, Rabin-Scott and autonomous machines. Descriptions.
  2. Design of generalized registers.
  3. Design of a complete simple controller from FSM control unit and data path.
  4. Variants of systems similar to sorter: pipelined, butterfly, controllers.
  5. Specification of FSMs.
  6. Minimization of FSMs.

Homework 1.
  1. Create a state graph for any state machine that has some practical meaning. It may be a game such as "missionaires and cannibals" or "wolf, sheep, cabbage and man", or "tic-tac-toe". Describe the problem as a state machine. Minimize it.
  2. Minimize a randomly generated state machine which has about 509% of don't cares in transitions and outputs.


    Minimization, state assignment and realization of Finite State Machines.
      Mandatory Slides

    1. Minimization of FSMs. Incomplete tables of machines. Basic concepts. Compatible states. Inconsistent states. Incompatible states. Conditionally compatible states. Triangular table. A method to calculate MCCs. Minimization Algorithm. Covering condition. Closure Condition. Finding the final table. More examples. Sequence detector circuit synthesis. Algebraic method to find all MCCs.

    2. Advanced FSM minization and assignment. Graphical method to find all MCCs. One more tabular method to find all MCCs. Method based on Closure graphs to find best compatibles. Method based on maximum compatibles that combines state assignment with state minimization. More examples. Typical homework problems that may be assigned.

    3. FSM State Encoding. Models of sequential circuits. Methodologies. State Assignment Problem. State Assignment Strategies. One-Hot State Assignment. Heuristics for state assignment. General approach to heuristic state assignment. Output Based encoding. Kiss format example. Modern State Assignment approaches. Hypercube embedding methods. State Group identification. Representation of symbolic implicants. Minimization using Multiple-Valued Logic. State groups and group faces. Examples of hyper-cube embedding. Adjacency-Based State Assignment. Fan-out oriented rules. Fan-in oriented rules. Comparison of methods and discussion. Tools.

      Auxiliary Slides

    1. Rule Extraction from Recurrent Neural Networks. Interesting application of FSM Minimization. Thesis in PDF. There are many other applications of FSM minimization in compiler writing, knowledge acquisition, testing and identification, and digital design.


    State Assignment of FSMs. Advanced methods and partition theory.

      Mandatory Slides

    1. Rule based state assignment. Synchronized Flip-Flops. FSM performance. FSM equations. Example of Modulo 5/3 Counter with hold. Derive equations directly from the FSM graph. FSM state assignment. Methods that derive codes directly from graphs. Rules. Explanation of rules.

    2. State assignment using-multiline and partitions. Definition of partition pair. Finding predecessor and successor partitions from maps and tables. Multi-line method for state assignment. Graphical operations on partitions. Main Theorem that links partitions from pairs to costs of excitation functions. Creation of the partition pair graph - systematic method. Finding best subsets of the graph. Role of partitions with substitution property (closed partitions) and partitions based on inputs 1 --> tau. Selected partitions. Generalization to JK flip-flops.

    3. Example of state assignment using rules. Comparison of methods on a simple example.

    4. Encoding based on partitions. Encoding based on partitions. Finding all or some closed partitions from a graph. Intuitive encoding of a counter. Examples. Relations between partitions and costs of logic functions.

      Auxiliary Slides - more examples.
    1. Slides in PDF on FSM design.


    Design of FSM from Flowcharts and similar techniques.

    Mandatory Slides

  1. Addition and Subtraction with Signed-Magnitude Data. PPT slides from Mano. Use of flowcharts. This is the very simple example illustrating use of flowcharts in design of data path and control unit.

  2. Ciesielski. RTL design. Slides in PDF. Here you find more complicated examples, also based on Mano book.

  3. Slides in PDF. Control logic design by Ciesielski. Here is a complete example without using invariants.

  4. Marek Perkowski et al. Automatic Design of Finite State Machines with Electrically Programmable Devices. Paper in PDF. This is a description of using invariants in FSM design. Also it includes simple explanation of Mealy-Moore and Moore-Mealy convertions. You do not have to learn stuff from this paper that was not discussed in the class.

  5. Marek Perkowski. Symbolic Analysis of Sequential and Parallel Program Schemata in the Digital Design Automation System. Paper in PDF. This paper has several good examples of controllers that illustrate the usefulness of algorithmic transformations and calculating invariants. You do not have to learn about formal verification aspects.

  6. FSM implementation in VHDL. PPT slides. Importance of good versus bad documentation of code in VHDL.

    Auxiliary Slides

  7. Slides in PDF on Design using flow-charts. Addition and subtraction, flowcharts. Operations in Signed 2's complement. Multiply Signed Magnitude. Multiply Signed-2's Complement. Array multiplier. Divide Fixed-Point Signed-Mag. Flowcharts. Floating point operations and flowcharts. Division. Booth multiplication algorithm. BCD adder. BCD subtraction. Decimal Arithmetic unit. Parallel Decimal Addition. Serial algorithms. Decimal multiplication flowchart. Decimal Division Flowchart.

  8. Slides in PDF from Mano about basic design on RTL level using flowcharts. Instruction Code. Stored Program Organization. Address Type. Basic Computer Registers. Common Bus. Address register. Accumulator. Timing. Basic Instruction formats. Completeness of instructions. Control unit. Sequence Counter. Instruction Cycle. Fetch and decode. Fetch phase. Instruction cycle flowchart. Instruction paths. Register-reference Instructions. Memory reference instructions. Branching. Input and output registers and configurations. Interrupts. Detailed control unit design example.

  9. Davis. State Machine Design methods. Flowcharts. Slides in PDF> ASM/Flow diagram based methods. Components of FSM model. Moore machines. Mealy model. Example of traffic control FSM. State graphs, state tables and flowcharts. Relations and timing. ASMs and Sequence Diagrams. Reduction. Concurrency. Sequencing Patterns in FSM design. Pipelining. Handshaking. Arbitration.

  10. Sequencing and Control. Slides in PPT. Fundamental. Datapath and control. ASM. Timing in ASM. ASM examples. Binary Multiplier. Hardwired control. Control Design methods. Sequence register and decoder. One flip-flop per state. Microprogrammed control.

  11. Slides in PPT. Instructions in microprocessor. Addressing modes. ISA. Instruction Set Architecture. LC-3 overview. Memory and registers. Instruction set. Graphic illustrations of data movement. Relative addressing. Indirect Addressing. Base and offset addressing. Control instructions. Branching. Jumps and traps. Complete data path. Data Path components.

  12. Slides in PDF in control unit design using flowchart and HDL. On exploring algorithm performance between Von_Neumann and VLSI Custom_Logic Computing architectures. Microprocessors versus Custom Logic Computing Systems. General Microprocessor Architecture. Mapping Algorithms to VLSI Architecture. VLSI Systems modeling. ASM charts. Counting cycles in custom design. Benchmarking. Comparing cycle counts. Comparing complexity.

  13. Lectures on Assembly Language for Intel Based computers. FSM. While Operator. Flow-charts. Slides in PPT. Implementing FSM in assembly level code. MASM. Operations. Flowcharts.

  14. Slides in PDF> Special Topics in Advanced Digital System Design. Boards and tools. Design considerations and real-life design. Design methodologies and design specifications. Design for testability. BIST. Virtex II, Xilinx MicroBlaze. Boards.

  15. Mano Chapter 8. Slides in PPT about flow-charting and control design. Microprogrammed control. Control of processor unit. Microprogram examples. Design Example: Binary Multiplier by Hardwired Control. Hardwired Control for Multiplier. Example of Simple Computer. Design of Simple Computer. Control Logic. Typical Complete project.

  16. Slides in PPT about Multi-cycle control. The Multi-Cycle Implementation. The Five Cycles. Complete multi-cycle datapath. Summary of execution steps. Instruction fetch. Control for IF Cycle. Cycle 2: Instruction decode. Instruction decode cycle. Control for first two cycles. Cycle 3: Execute. FSM state for cycle 3 of beq. R-type instructions. R-type execution. R-type execution and write back. FSM states for R-type instructions. Load and store. Cycle 3 for lw and sw: address computation. Cycle 4 for store: Memory access. Cycle 4 for load: Memory access. Cycle 5 for Load: Write Back. Memory Instruction states. Conditional Branches and Jumps. Branch and Jump Addressing Modes. Cycle 3 for Jump. Control of multicycle implementation. Complete FSM. Implementing the FSM in hardware. ROM implementation. Discussion. Multi-cycle CPU Key Points.

  17. Lecture on DSP processor fundamentals. PDF format. DSP Processors. Embodiments. and Alternatives. The most important features. DSP cores. DSP core based ASICs. Customizable DSP Processors. Alternatives to Commercial DSP Processors.

  18. Timing of FSM and FFs. Slides in Postscript.

  19. Mano. Slides in PDF on assembly leved processor design. Programming the Basic Computer. Instructions and their formats. Binary and assembly languages. Assembly Language. Asseblers. Program Loops. Programming arithmetic and Logic Operations. Subroutines. Input-Output Programming.

    Midterm 1.
  1. Midterm 1 from year 2006.


    Decomposition of Finite State Machines. Serial and Parallel Decomposition. Links to Encoding.

      Mandatory Slides

    1. Introduction to FSM Decomposition. Reminder of encoding. Partitions. Partitions with Substitution property. Main theorem. Why decomposition? Serial Decomposition. Parallel decomposition. Detailed Example of Serial Decomposition. Example of parallel decomposition. Other types of decomposition.

    Behavior, experiments, testing, and verification of FSMs.

      Mandatory Slides

    1. Introduction to experiments with Finite Automata. Algorithms to generate Distinquishing, Homing, and Synchronizing Sequences. State table verification for sequential circuit. Algorithm to generate a distinquishing sequence. Transfer sequence. Distinquishing sequence. Synchronizing sequence. Designing checking experiments. Initialization. Identification. Transition Verification. Complete example. DFT for sequential circuits. Construct testing graph. Definitely diagnosable machines. Random testing.

    2. Examples of homing and synchronizing experiments. Homing sequence, to identify the final state. Synchronizing sequence.

      Auxiliary Slides

    1. Advanced FSM Decomposition Theory. Ordering and bounds. Orderings on Inclusion Relations. Ordering on Inclusion Relations. Partially Ordered Sets (POSETS). Hasse Diagram. POSET examples. Least Element. Lower Bound. Lower Bound Example. Greates Lower bound. Example. Upper Bound. Example. Least upper Bound. Example. Bounds. Lattices. Properties of lattices. Partial Ordering of partitions. Trivial partitions. Machine Lattice Example. Operations on Partitions. Meet and Join of two partitions. Partition Operation Properties. Parallel Decomposition. Parallel decomposition theorem. Example.

    2. Lecture in PDF on Testing and Testable Design of Digital Circuits. Overview. Motivation and introduction. An example. Sequential Circuit model. Fault model. Theory. Checking experiment design. Summary.

    3. Randomized Parallel Algorithms for the Homing Problem. Paper in PDF. Research paper by Ravikumar and Xiong. Randomized Parallel Algorithms for the Homing Sequence Problem.

    4. Homing and Synchronizing Sequences. Slides in PDF. Motivations. Definitions and examples. Algorithms: current state uncertainty, computing homing sequences, Computing synchronizing sequences. Variations. Adaptive homing sequences. Computing shortest sequences. Parallel algorithms. Difficult related problems.

    5. Slides in PDF. Principles and Methods of Testing FSM - A Survey. Background. Five Fundamental problems. Problem 1: determining the final state after test. Problem 2. Identify the unknown initial state. Problem 3: State Verification. Problem 4: Conformance testing. Conclusion.

    6. State Identification; homing, synchronizing and distinquishing sequences. Slides in PDF. State Uncertainties. Homing Sequence. Example. Synchronizing Sequence.

    7. Slides in PPT on Algorithmic Testing. Why Testing. Testing of black box FSM. Why Deterministic Machines. Determinism. Preliminaries: Separating sequences. A: separate to blocks of states with different output. Repeat B: Separate blocks based on moving to different blocks. Want to know the state of the machine. HOming sequence. Example of homing sequence. Synchronizing sequence. State Identification. Sometimes cannot identify initial state. Conformance testing. Check conformance with a given state machine. Preparation: Construct a spanning tree. How the algorithm works. Combination lock automaton. When only a bound on size of black box is known. Conformance testing algorithm. Model Checking. Buchi automata. Examples. System. Model Checking/Testing. Black Box checking. Experiments. Simpler problem: Deadlock. Deadlock complexity. Modeling black box checking. Games of incomplete information. Modeling BBC as games. A naive strategy for BBC. On the fly strategy. Learning an automaton. A strategy based on learning. Complexity. Some experiments. Part 2: software testing. Some software testing stages. Some drawbacks of testing. Black-Box (data-driven, input-output) testing. White box testing. Some testing principles. Inspections and walk-throughs. Code inspection. Checklist for inspections. Walkthrough. Selection of test cases (for white-box testing). Cover all the path of the program. How to cover the executions. Statement coverage. Execute every statement at least once. Decision coverage. Each decision has a true and false outcome at least once. Condition coverage. Multiple condition coverage. Relativizing assertions. Verification conditions. How to find values for coverage. How to find a flow chart. Test cases based on data-flow analysis. Test case design for black box testing. Equivalence partition. Example: a legal variable. Boundary value analysis. Test case generation based on LTL specification. Goals. Divide and conquer. Spec. Example: GCD. Why use Temporal specification. Potential explosion. Use of software: snapshots. Drivers and stubs.

    8. Testing of Digital Circuits. Slides in PPT. Design approaches. Faults: sources and types. Fault models. Combinational Circuits: Test Pattern Generation. Fault Simulation. Test Generation. Limitations. Typical Circuit Enhancements. Parallel fault simulation. Example. Deductive fault simulation. Example. Boolean Difference. Example. D-Algorithm. Singular cover. D-Intersection. Primitive D-Cube of fault. Propagation D-Cube. D-Algorithm steps. PDCF example. D-Drive example. Consistency example. Testing techniques. State Table Verification. Homing and Distinguishing sequence. Example. Random testing. Transition count testing. Scan based testing. Signature analysis. PRBS generator. BIST example. BIST register modes. BIST steps: example.

WEEK SIX. February 12 - February 17.

    Asynchronous Automata.
      Mandatory Slides
    1. Introduction to asynchronous Automata. Feedback Model for asynchronous Sequential Networks. Fundamental Mode Asynchronous FSM. Asynchronous Design Difficulties. Stable States. Races. Types of races. Asynchronous FSM Benefits. Example. Next state variables. Asynchronous state tables. Constraints on asynchronous networks. Many Examples. Race conditions. Examples. Avoiding race. Hazards. Steady State hazards. Hazard example: Feedback sequential implementation. Essential hazard.

    2. Realization of asynchronous automata. Design of asynchronous circuits. Reduction of pseudo-equivalent states and equivalent states. Reduction of compatible and pseudo-equivalent states. Moore machine. Mealy Machine. Outputs in Moore and Mealy Machine. Encoding an asynchronous machine. Races. Elimination of races by cyclic coding. Realization of memory and outputs. Encoding. Realization with Ffs and feedback loops. Realization using logic gates. Use of tools. Mealy and Moore machines.

    3. Marek Perkowski. Basic Asynchronous circuit design. File in PDF. This is my text with many problems solved and examples of problems from exams.

WEEK SEVEN. February 19 - February 24.

    Asynchronous Automata. Asynchronous Systems.
      Mandatory Slides
    1. Metastability. Asynchronous Input example. Metastability. Why Metastability is a "special" problem. Metastability in D FFs. Analyzing metastability. Metastability test circuit. Application example. Synchronizer circuits.

    2. Self-timed asynchronous machines. Self-timed circuits. Simple handshake example. How to apply to clocked systems. Phased logic concepts. LEDR encoding. Phased Logic AND gate. Phase logic Gate Timing with multiple outputs. Phased logic gate firing rules. Correspondence between phases and tokens. Example of token movement. Initial token Markings. Life and Safe Initial Token Marking. Liveness and Safety Theorems. Phased Logic Synthesis.

    3. Design of self-synchronized state machines. Loc Bao Nguen, Marek Perkowski and Lech Jozwiak, Design of Self-Synchronized Component FSMs for Self-Timed Systems. Paper in PDF.


    1. Scott Hauck. Asynchronous Design Methodologies: An Overview. Paper in PDF.

      Design of large asynchronous controllers.
    2. Slides in PPT. Lecture on Direct synthesis of Large-scale asynchronous Controllers using a Petri-Net-based approach. Motivation. Design Flow. Verilog VHDL specification. Petri Nets and Trace Expressions. Synthesis Process. Conclusion.

    3. Slides in PPT. Advanced Tutorial Lecture on Hardware Design of Asynchronous Systems and Petri Nets. Introduction. Modeling Hardware with Petri Nets. Synthesis of Circuits from Petri Net specifications. Circuit verification with Petri Nets. Performance analysis with Petri Nets.

    4. Yakovlev slides in PPT on Asynchronous Technology. Design Productivity Gap. Design costs and time to market. Timing Problems. Self-Timed Systems. The Timing Mode Spectrum. GALS module with stoppable clock. GALS: Petri Net model. Backend language: Petri Nets? New Design Flow; two-level control. Direct mapping of Petri Nets; event-based and level-based. Direct mapping of STGs. Case Studies.

    5. M.S. Thesis on Design and Implementation of an Asynchronous Pipelined Fast Fourier Transform Processor. Thesis from Linkoeping by Jonas Claeson.

    MIDTERM 2.
      Mandatory Slides
    1. Midterm 2.

    Cellular Automata.
      Mandatory Slides
    1. Introduction to Cellular Automata and Artificial Life. Conway's Game of Life. Cellular Automata. Self Reproduction. Universal Machines. Artificial Life. Idea of Cellular Automata. Simulation Goals using Cellular Automata. Various types of Arrays. Rules for cells. Interaction is local. Neighborhood. States of Cellular Automata. Simple 1-Dimensional Cellular automata and patterns. Classification of CA. Automata Theory and CA formalism. Local Dynamics. Global Dynamics. Links to dynamical systems. Work of Wolfram. Classification of CA. Complexity of rules. History of CA research. Self-reproduction and Von Neumann. Examples of dynamical systems. Research questions. Homework questions and research problems for students.

    2. Cellular Logic Illustrations. Here we give few snapshots of the 3D cellular automaton FPGA-based supercomputer realized in Japan - The Brain Machine.

    3. Quantum Dot Cellular Automata. Quantum Dots. What are they? why are they important? Mass production and patterning of quantum dots. The four dot device. Quantum Dots as Cellular Automata. Five dot model of Lent and Porod. Quantum Dot Wire. Example of complete geometrical-logical system for QD. Quantum Dot Inverter. Quantum Dot Majority Gate. Special cases of majority. Quantum Dot Logic Gates that use NOT. Layout of large QD circuits.

    4. Cellular Morphogenesis. Morphogenetic modeling. Dynamical Systems. Spaces and geometries. Aspects of Discretization. One-Dimensional CA. Effects of simplification. Wolfram's 1D CA. CA rules based on Symmetry. Rules encoding. Temporal Evolution. Metaphor for morphogenesis. CA rule mutations. Predictability. Aspects of CA morphogenesis. Patterns and morphology.n

    Cellular Automata Project.
      Mandatory Slides
    1. Some project information on Cellular Automata. Examples of past projects.

WEEK EIGHT. February 26 - March 3.

    Cellular Automata in Physics. Reversible Cellular Automata. Simulations in biology and social life.
      Mandatory Slides
    1. Cellular Automata models in Engineering. Cellular Automata versus Genetic Algorithms. Sipper rules for Cellular Automata. Advantages of CAs. Applications of CAs. Possible homeworks on CAs. How to study behavior of CAs. Typical rules and their analysis. GA for majority - example. Other examples.

    2. Reversible Cellular Automata. Random Number generation. Comparison with LFSR. Hybrid Cellular Automata. Analysis and Comparison. CA-based Cipher Systems. CA Block Ciphers. Computation with CA. Reversible logic and Reversible cellular automata. Examples. Blocking. Reverse behavior. A Billiar Ball Model of Computation. Modeling in CA. Possible homeworks and research.

    3. Physical Reversible Models of Cellular Automata. Physics becomes a computer. Emulating Physics. Conway's Game of Life in new perspective. Reversibility and other conservations. Adding Convservations to CA model. Diffusion Rule. Toffoli-Margolus Gas rule. Lattice gas refraction. Lattice gas hydrodynamics. Dynamical Ising Rule. Bennett's 1D rule. 3D Ising with heat bath. 2D "Same" rule. 3D Same rule. Reversible aggregation rule. Adding forces irreversibly. Conservations summary.

WEEK NINE. March 5 - 10.

    Reversible Cellular Automata. Artificial Life. Simulations in biology and social life.
      Mandatory Slides
    1. Part 2 of Physical Reversible Models of Cellular Automata. Review. CA with conservations. Physical Worlds. Computational Universality. What's wrong with Life. Billiar Ball model reminded. A BBM CA rule. The Critters rule. "Critters" is universal. UCA with momentum conservation. SSM collisions on other lattices. Getting rid of mirrors. Realization of Fredkin gate. Macroscopic Universality. Relativistic conservation.

    2. Part 3 of Physical Reversible Models of Cellular Automata. Spatial Computers. CAM-8 programming model. Lattice example. Materials simulation. Logic simulation. Porous flow. Image Processing. FPGA and DRAM models. SPACERAM: a general purpose crystalline lattice computer. Mapping lattices to hardware.

    3. Artificial Life. Artificial life - Von Neumann's Automaton and Viruses. States in Von Neumann Automaton. Ordinary Transmission States. Quiescent State. Confluent States. Pulser. Decoder. Repeater. Special Transmission States. Sensitive States. The Sensitized Tree. Periodic Pulser. Coded Channel. Transition and Output Table. Finite Automaton. Constructing Arm. Horizontal Advance. Constructing Arm. Reading Loop. Virus Categories. Computers and Biology. Viruses and Life.

    4. Cellular Automata Model for Fish and Shark. Simple rules for Predator/Prey Relationships. Rules for an example of biological simulation. Initial Conditions. Breeding rules. Fish Rules, Shark rules. Shark random death. Programming Logic. Sample C++ code. Parallelism. Boundary values. Simulation of generations. Long-term trends. Variations of initial conditions. Very small populations. Parallel performance. Speed-up.

WEEK TEN. March 12 - 17.

Basic concepts of Sequential State Machine Theory. Non-deterministic and deterministic automata.
    Mandatory Slides
  1. Set Theory and Introduction to State Machine Theory. Why Sequential Machine Theory. Hardware/software. Formal Languages. Finite State Machines. Goal of this set of lectures. Turing machines and automata applications and role. Types of Machines. Review of Set Theory. Special Sets, relations. Domain and Range of a relation. Functions and mappings.

  2. Equivalence. Nondeterministic and Deterministic Finite Automata. Equivalence relation. Examples. Inclusion Relation. Partition Notation. Relations may be orderings. Partial Orderings. Properties of partial orderints. Total Orderings. POSETs. Finite Automata and Language Recognizers. Kleene Star. Kleene Closure. Strings and recognizers. State transitions. Recognizer as a directed graph. Examples of recognizers. Rabin-Scott machines. Non-Deterministic FSMs. DFA-NDFA theorem. NDFA example. NDFA to DFA. Lambda strings and multiple transitions. State equivalents. Creating new machines. Comparison of machines.

Regular Languages versus automata. Complete design procedure starting from regular expressions.
    Mandatory Slides
  1. Regular Languages and Regular Expressions. Formal Languages. Regular Languages. Alphabets and strings. Kleene Closure. Concatenation operator. Classes of Languages. Rule based Languages. Kleene Star. Examples. Kleene Closure. Recursive Language definition. Examples. Principle of Mathematical Induction. Examples. Regular Expressions. Notation. Regular Languages. Typical homeworks and problems.

  2. Deterministic and Nondeterministic Finite Automata. Numerical Acceptor. Languages Accepted by FA. Union and Concatenation on languages. Other operations. Context Free Languages. Example of Non-regular language. Context free grammars. Definitions of context free grammars. Context free languages. Pushdown automata. Pushdown relation. PDA properties and notation. PDA recognizer. Examples. Checking acceptance.

  3. Regular Expressions. Regular Expression Manipulation model. Null machine. Reachability Analysis. State Diagram Manipulation. The complement machine. Language Decidability. Language Overlap. DeMorgan's theorems. Regular Expression equivalence. Examples. Reduction. Mealy and Moore Machines. FSMs and clocks. Sequence detectors. Sequential Machine Problems. Recursive Definitions of Delta and other functions. Possible exam problems.

  4. Behavoral Equivalence. Mealy and Moore Automata. Behavioral equivalence. Examples. Equivalence of outputs. Verifying Morphisms. How to check behavioral equivalence of Mealy and Moore. Mealy to Moore conversion.

  5. Morphisms of Machines. Homomorphisms, epimosphisms, isomorphisms. Free Semi-Group. Strings. Partitions. Types of relations. Grupoids. Semigroup. Closed Binary operation. Monoid. Group. Morphisms. Homomorphism. Homomorphism of groups. Endomorphism. Semi-group homomorphism. Homomorphism of monoids. Isomorphism. Graphical illustrations of morphisms. Machine Isomorphisms. State and Output Isomorphisms. Homo- versus Iso-morphisms of machines. Output equivalence. Inverse Machine Isomorphism. Machine Equivalence. Behavioral Equivalence of two state machines. Homeworks.


    Mandatory Slides
  1. Overview of Design Automation for Sequential Circuits and Systems. Moore's Law. Microelectronic Circuits. Microelectronic Design Styles. Standard Cells. Array-Based Design. Semi-custom style trade-off. How to deal with design complexity. Abstractions and abstraction levels. Design Domains and Levels of abstractions. Design versus Synthesis. Synthesis process. Architecture design. Behavioral description and its Control Data Flow Graph (CDFG). Design Space and Evaluation Space. Optimization Trade-off in Sequential Circuits. Architectural Design Space Example. Design Automation and design tools.

  2. Presentations of projects.
  3. Additional midterm exams 1 and 2 (you can improve your grade, but for not as many points as writing it right the first time).
  4. Return complete report on project on March 25. Final date.


Design of fuzzy logic controllers.
  1. PDF slides. Wang and Kazmierski. VHDL-AMS based genetic optimization of a fuzzy logic controller for automotive active suspension system.

Design of large controllers and spectral methods.
  1. Paper in PDF. The hardware implementation of real-time SAR signal processor.

  2. Contents of DSP book. PDF.

  3. Embedded System architectures paper in Postscript.

  4. Shi. Ph.thesis in PDF. Floating-point to fixed-point conversion.

  5. Westerlund. Comparison of Synthesizable Processor Cores. M.S. Thesis in PDF.

  6. Student Project in PDF. A System on a Chip for Audio Encoding.

  7. M.S. Thesis by Kishore Kotteri in PDF. Optimal Multiplier Less Implementation of the Discrete Wavelet Transform for Image Compression Applications.

  8. MS Thesis Kurt Rogers in PDF. Acceleration and Implementation of a DSP Phase-Based Frequency Estimation Algorithm. Matlab and Simulink to FPGA via Xilinx System Generator.

  9. Using Delayed Addition Techniques to Accelerate Integer and Floating-Point Calculations in Configurable Hardwarea. Paper in PDF.

  10. Paper in PDF on Programmable Digital Signal Processor.

  11. Thesis in PDF. Orientation Filters for Real-time Computer Vision Problems.

  12. M.S. Thesis by Tyler Moeller in PDF. Field Programmable Gate Arrays for Radar Front-End DSP.

  13. Vector Processors.mht

  14. M.S. Thesis by A. Walters in PDF. A Scaleable FIR Filter Implementation Using 32-bit Floating Point Complex Arithmetic on a FPGA Based Custom Computing Platform.

  15. M.S. Thesis in PDF by Belanovic. Library of Parametrized Hardware Modules for Floating-Point Arithmetic with An Example Application.

  16. Thesis by David Chui on Using FPGA engines in Physics.

  17. V. Arkesh. FPGA Implementation of a Low Power Doppler Invariant BSK Receiver.

  18. DSP systems. Paper in PDF.

  19. Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor. Text in PDF.

  20. Peterson. Text in Postscript. An Assesment of the Suitability of Reconfigurable Systems for DSP.

  21. High Performance DSP. Text in PDF.

  22. Bass. A Low-Power, High-Performance, 1024-Point FFT Processor. Text in PDF.

  23. MS Thesis in PDF on Adaptive Computing in NASA Multi-Spectral Image Processing.

  24. Postscript text on An Assesment of the Suitability of FPGA-based Systems for use in DSP.

  25. Blair text in Postscript. A review of DFT.

  26. MS thesis by Ramirez Silva in PDF. On Implementing Time-Frequency Representations on Hardware/Software Computational Structures for SAR Applications.

  27. Tom Curtis on Sonar Technology. Past and Current. Text in PDF.

  28. Broadcast transmission. Slides from Xilinx. PDF format.

Radon Transform.
  1. Coric. Thesis on Parallel-Beam Backpropagation: an FPGA Implementation Optimized for Medical Imaging. This includes Radon Transform.


FFT Processors.
  1. Literature in Word on applications of FFT.

  2. M.S. THESIS on Development and Verification of Parametrized Digital Signal Processing Macros for Microelectronic Systems. FFT related. PDF format.

  3. Slides in PPT on Sharpening Techniques for Sensor Feature Enhancement. Applications of FFT etc. DSP methods.

  4. Patent by Sharp on FFT processor. PDF document.

  5. M.S. thesis in PDF on An Approach to Low-Power, High-Performance, Fast Fourier Transform Processor Design.

  6. He and Torkelson. Design and Implementation of a 1024-point Pipeline FFT Processor. Paper in PDF.

  7. A Pipeline FFT Processor. Paper in PDF.

  8. A 2048 Complex Point FFT Processor Using a Novel Data Scaling Approach. Paper in PDF.

  9. A DWT-DFT Composite Watermarking Scheme Robust to Both Affine Transform and JPEG Compression. Paper in PDF.

  10. Efficient Cordic Designs for Multi-Mode OFDM FFT. Paper in PDF.

  11. A High-Performance Radix-2 FFT in ANSI C for RTL Generation. Slides in PPT.

  12. Automation Techniques for Fast Implementation of High Performance DSP Algorithms in FPGAs. Slides in PPT.

  13. Matlab Extensions for the Development, Testing, and Verification of Real-time DSP Software. Slides in PPT.

  14. Embedded Computing DSP. Slides in PDF.

  15. A Practical Example of DSP System Design, ADSL Modem DMT Engine. Slides in PPT.

  16. DSP Microprocessors, Software and Applications. Slides in PPT.

  17. Unitary Transforms. Slides in PPT.

  18. Fast Fourier Transform Implementation Using Field Programmable Gate Array Technology for Orthogonal Frequency Division Multiplexing Systems. M.S. Thesis in PDF.

  19. Generalized transforms for DSP generalized spectral analysis.mht

  20. The FFT on Graphics Hardware. Slides in PPT.

  21. Lecture. Introduction to FFT. Slides in PPT.

  22. Arvind. An Hardware Inspired Model for Parallel Programming. Slides in PDF.

  23. Lecture in PPT on Some Properties of the 2-D Fourier Transform.

  24. Slides in PPT on Image Pyramids.

  25. High Level VHDL modeling. FFT. Thesis in PDF.

  26. Slides in PPT. Image Processing and Convolution.

  27. Slides in PDF. The Fourier Transform.

  28. Full Search Content Independent Block Matching Based on the Fast Fourier Transform. Paper in PDF.

  29. A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications. Paper in PDF.

  30. Investigation of a phase only correlation technique for anatomical alignment of portal images in radiation therapy. Paper in PDF. This paper was referenced by a paper that presents quantum and classical matching based on FFT.

  31. Slides in PPT on Implementation of DFT on a Reconfigurable Processor.

  32. Shirazi Implementation of a 2-D Fast Fourier Transform on a FPGA_based Custom Computing Machine. Paper in PDF.

  33. Power Point Slides on Efficient FFT on VIRAM.

  34. Applications of Fourier Theory. Template Matching. Slides in PDF.

  35. Optimized Implementation of Speech Processing Algorithms. Applications of DSP and FFT. Paper in PDF.

Accuracy. Arithmetics.
  1. Literature in Word on applications of FFT.

  2. Automatic VHDL Model Generation of Parametrized FIR Filters. Paper in PDF.

  3. Automating Transformations from Floating Point to Fixed Point for Implementing DSP Algorithms. Slides in PPT.

  4. Data Smoothing. Slides in PPT.

  5. Fixed Point Effects in Digital Filters. Slides in PDF

  6. Wordlength Optimization with Complexity and Distortion Measure and Its Application to Broadband Wireless Demodulator design. Slides in PPT.

    Spectral Methods.
  1. Thesis in Postscript. Thornton. Spectral Based Numerical Methods for Combinational Logic Synthesis.

  2. Farsi Handwritten Word Recognition Using Continuous Hidden Markov Models and Structural Features. Thesis in PDF.

  3. Faster than FFT. The Chirp-Z RAG-n DFT. Text in PDF.


State Minimization
  1. Robert Fuhrer. Sequential Optimization of Asynchronous and Synchronous FSMs: Algorithms and Tools. Thesis in PS.

  2. Marek Perkowski. Digital Design Automation: Finite State Machine Design. Paper in PDF.

  3. Richard Puri. An Efficient Algorithm to Search for Minimal Closed Covers in Sequential Machines. Paper in PDF.

  4. Paper by Avedillo in PDF. A new method for state reduction of incompletely specified FSM.

  5. Perkowski. Digital Design Automation: FSM design. Paper in PDF.

  6. Rho, Hachtel and Somenzi. Paper in PDF. Exact and Heuristic Algorithms for the Minimization of Incompletely Specified State Machines.

  7. Avedillo, Quintana, Huertas, New Approach to the State Reduction in Incompletely Specified Sequential Machines. Paper in PDF.

  8. Avedillo, Quintana, Huertas, Efficient State Reduction methods for PLA-based sequential circuits. Paper in PDF.

Concurrent State Minimization and State Assignment
  1. Perkowski and Zhao. Concurrent Two-Dimensional State Minimization and State Assignment of Finite State Machines. Paper in PDF.

  2. Avedillo, etc. A New Method for the state reduction of Incompletely Specified Finite Sequential Machines. Paper in PDF.

  3. Avedillo, Quintana, Huertas, State Merging and state splitting via state assignment: a New FSM synthesis algorithm. Paper in PDF.

  4. Avedillo, Quintana, Huertas, SMAS: A program for the Concurrent State Reduction and State Assignment of Finite State Machines. Paper in PDF.

  5. Calazans under Davio. PHD. State Minimization and State Assignment of Finite State Machines: their relationship and their impact on the implementation. PHD Thesis in PDF.

  6. Calazans, paper in PDF. Considering State Minimization during State Assignment.

Examples of Big Asynchronous State Machine Designs
  1. Kida and Perkowski. The Cube Calculus Machine. A Ring of Asynchronous Automata to Process Multiple-Valued Boolean Functions. Paper in PDF.

Some Interesting FSM Design Ideas.
  1. Finite State Dynamical Systems and Finite Automata. WWW page.

  2. Sequential Circuit Design for Space-Borne and Critical Electronics. Slides in PPT.

  3. State Machine Design. mht

  4. Random Thoughts on Abstract Machines. Paper in PDF.

Quantum State Machines and Quantum Sequential Circuits
  1. Blind Encoding into Qubits. Paper in PDF.

  2. Quantum Walks, Quantum Gates and Quantum Computers. Paper in PDF.

  3. Deutsch's Universal Quantum Turing Machine (Revisited). Paper in PDF.

  4. Quantum Finite Automata and Weighted Automata. Paper in PDF.

  5. Quantum Multiplexing for Quantum Computer Networks. Paper in PDF.

  6. Some Observations on Two-Way Finite Automata with Quantum and classical states. Paper in PDF.

  7. Nuclear Spins as a Quantum Memory in Semiconductor Nanostructures. Paper in PDF.

  8. Paper in PDF. Operation of a 1-bit Quantum Flux Parametron Shift Register.

  9. Rapid Single-Flux-Quantum Dual-Rail Logic for Asynchronous Circuits. Paper in PDF.

  10. Cheng and Wang. Grammar Theory Based on Quantum Logic. Paper in PDF.

  11. Quantum Neurons and their Fluctuations. Paper in PDF.

  12. Tools for the Computer-Aided Design of Multigigahertz Superconducting Digital Circuits. Paper in PDF.

  13. A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram. Paper in PDF.

  14. Self-Timed Parallel Adders based on DI RSFQ Primitives. Paper in PDF.

  15. Towards a Systematic Design Methodology for Large Multigigahertz Rapid Flux Quantum Circuits. Paper in PDF.

  16. New BSFQ Circuit Designs with Wide Margins. Paper in PDF.

  17. Tsai and Kuo, Quantum Boolean Circuit Construction and Layout under Locality Constraint. Paper in PDF.

  18. Tsai, Kuo, Wei. Quantum Boolean Circuit Approach for Searching an Unordered Database. Paper in PDF.

  19. A Novel Global Self-Timing Methodology for BSFQ Circuits. Paper in PDF.

  20. Wang, Lu, Tsai, Kuo, Modified Karnaugh Map for Quantum Boolean Circuit Construction. Paper in PDF.

  21. A Quantum Particle Swarm Optimization. Paper in PDF.

  22. Lu, Wang, Kuo. Quantum Boolean Circuits Construction Using Tabulation Method. Paper in PDF.

  23. Wang, Lu, Kuo. An Efficient Functional Verification Method for Quantum Boolean Circuits. Paper in PDF.

  24. Chang and Cheng. Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. Paper in PDF.

  25. Childs, Bacon, Wim Van Dam. From Optimal State Estimation to Efficient Quantum Algorithms. Slides in PDF.

  26. Dimitri Petritis. Sequential and Asynchronous Processes Driven by Stochastic or Quantum Grammars and their Application to Genomics: A Survey. Paper in PS.

  27. Slides in PDF. Automatic Synthesis of Sequential Quantum Boolean Circuits Based on Self-Timed Specifications.

  28. Paper in PS. Tools and Applications II. The IF Toolset. UML and other tools.

  29. Modeling the operation of Margolus Quantum Cellular Automaton using high-level Petri nets. Paper in Postscript.

  30. Paper in PDF by V. Pratt. Chu Spaces: Automata with quantum aspects.

  31. Chu Spaces: Automata with Quantum Aspects. Paper in PS.

  32. Childs. Overview of adiabatic quantum computation. Slides in PDF.

  33. Margolus. Parallel Quantum Computation. Paper in PDF.

  34. Margolus. Quantum Computation. Paper in PDF.

  35. Childs and Wim van Dam. Quantum Algorithm for a Generalized Hidden Shift Problem. Slides in PDF.P

  36. Design and Implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram. Paper in PDF.

  37. A Basic Circuit for asynchronous superconductive logic using RSFQ gates. Paper in PDF.

  38. Design and Operation of a rapid single flux quantum demultiplexer. Paper in PDF.

  39. Design and Experimentation of BSFQ logic devices. Paper in PDF.

Multi-Valued Logic.
  1. Gao, Brayton, Mishchenko, Optimization of Multi-Valued Multi-Level Networks. Paper in PDF.

  2. Perkowski et al. Approaches to the Input-Output Encoding Problem in Boolean Decomposition. Paper in PS.

State Assignment and State assignment for Low Power.
  1. Ciesielski et al. A New State Assignment Technique for Testing and Low Power. Paper in PDF.

  2. Huertas and Quintana. Efficiency of state assignment methods for PLA-based sequential circuits. Paper in PDF.

  3. Multi-Criterial State Assignment for Low Power FSM Design. Paper in PDF.

  4. Patent on General base State Assignment for optimal massive parallelism. mht

  5. Designing Genetic Algorithms for the State Assignment Problem. Paper in PDF.

Asynchronous State Machines.
  1. Synthesis of Multiple-Input Change Asynchronous Finite State Machines. Paper in PDF.

  2. Asynchronous Logic. Paper in Word by Scott Mc Peak.

  3. Low Energy Asynchronous Adder. Paper in PDF.

  4. list of papers from conference.

  5. Marc RENAUDIN. Slides in PDF. Asynchronous Circuits Design.

  6. Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum. Paper in PDF.

  7. Locally Synchronous, Globally Asynchronous Design for Quantum-Dot Cellular Automata. Paper in PDF.

  8. A Framework for Component-based Construction Extended Abstract. Paper in PDF.

  9. Nowick. Automatic Synthesis of Burst-Mode Asynchronous Controllers. Paper in PDF.

  10. FSM Re-Engineering for Low Power State Encoding. Paper in PDF.

  11. Varshavsky - A Pioneer of Asynchronous World. Paper in PDF.

  12. Cheng and Pluna. Exact Essential-Hazard-Free State Minimization of Incompletely Specified Asynchronous Sequential Machines. Paper in PDF.

  13. Causal Dependencies in Parallel Composition of Stochastic Processes. Paper in PDF.

  14. R. Fuhrer, S. Nowick. Paper in Postscript. OPTIMISTA: State Minimization of Asynchronous FSMs for Optimum Output Logic.

  15. Liu. A State Variable Assignment Method For Asynchronous Sequential Switching Circuits. Paper in PDF.

  16. A CAD System for Automatic Synthesis of Generalized Asynchronous Circuits. Paper in PDF.

  17. Yun and Dill. Automatic Synthesis of 3D Asynchronous State Machines. Paper in PDF.

  18. Beni and Liang. Pattern Recognition in Swarms - Convergence of a distributed Asynchronous and Bounded Iterative Algorithms. Paper in PDF.

Asynchronous Cellular Automata.
  1. Asynchronous cellular automata and asynchronous automata for pomsets. Paper in PDF.

  2. Laying out circuits on asynchronous cellular arrays: a step towards feasible nanocomputers?. Paper in PDF.

  1. Hazard Detection by a Quinary Simulation of Logic Devices with Bounded Propagation Delays. Paper in PDF.

  2. Brunvald, Critical Hazard Free Test Generation for Asynchronous Circuits. Paper in PDF.

  3. Multi-Level Combinational Logic. Slides in PPT.

  4. Nowick. On the Existence of Hazard-Free Multi-Level Logic. Paper in PDF.

  5. Davis and Nowick. Paper in PDF. An Introduction to Asynchronous Circuit Design.

  6. Glitches and Hazards in Digital Circuits. Slides in PDF.

  7. Jacobson. M.S. Thesis in PDF. Asynchronous Circuit Design.

Rapid Protyping of Large Asynchronous Processors.
  1. Erik Brunwald. Tutorial Introduction to Asynchronous Circuits and Systems. Slides in PDF.

  2. Rapid prototyping Asynchronous Processor. Paper in PDF.

  3. Synthesis of Control Elements from Petri Net Models. Paper in PDF.

  4. Steve Furber. Principles of Asynchronous Circuit Design: A Systems Perspective. Paper in PDF.

  5. Scott Hauck et al. An FPGA for Implementing Asynchronous Circuits. Paper in PDF.

  6. Curtis Nelson. Technology Mapping of Timed Asynchronous Circuits. Paper in Postscript.

  7. L. Lavagno. Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs. Thesis in Postscript.

  8. Villiger. Slides in PDF. A Globally Asynchronous Locally Synchronous VLSI Circuit for the SAFER Cryptoalgorithm.

  9. Application of Synchronous Synthesis Tools for High-Level Asynchronous Design. Thesis in Postscript.

  10. Slides in PPT. Direct Synthesis of large-scale asynchronous controllers using a Petri-net-based approach.

  11. Asynchronous VLSI design chip. Thesis in PDF.

  12. Slides in PPT. Cortadella et al. Introduction to asynchronous circuit design: specification and synthesis.

  13. Slides in PPT. Cortadella et al. Introduction to asynchronous circuit design: specification and synthesis.

  14. Slides in PPT. Nelson. Technology Mapping of Timed Asynchronous Circuits.

  15. Paper in PDF. Asynchronous Early Output and Early Acknowledge Dual-Rail Protocols.

  16. Asynchronous Wrapper for Globally Asynchronous Locally Synchronous Systems. Thesis in PDF.

  17. Kondratyev. Logic Decomposition of Speed-Independent Circuits. Paper in PDF.

  18. Automatic Technology Mapping for Asynchronous Designs. Thesis in PDF.

Use of Petri Nets.
  1. Yakovlev. Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets. Paper in PDF.

  2. Kondratyev, et al. The Use of Petri Nets for the Design and Verification of Asynchronous Circuits and Systems. Paper in PS.

  3. Kondratyev. Paper in PDF. Design of Asynchronous Circuits Using Synchronous CAD Tools.

Asynchronous Systems in FPGAS.
  1. Mocho. Paper in PDF. Asynchronous Circuit Design on Reconfigurable Devices.


  1. Mishchenko. Slides in PDF. DAG-Aware AIG Rewriting. A Fresh Look at Combinational Logic Synthesis.

  2. Zhang. Mishchenko. Linear Cofactor Relationships in Boolean Functions. Paper in PDF.

  3. FRAIG: A Unifying Representation for Logic Synthesis and Verification. Slides in PDF.

  4. Introduction to Digital Circuits. Slides in PDF.

  5. Niklas. IWLS 2006. Mishchenko. Improvements to Combinational Equivalence Checking. Paper in PDF.