ECE 590. DIGITAL SYSTEM DESIGN USING HARDARE DESCRIPTION LANGUAGES.

1. ECE 271. Digital System Design. Second class in digital design at PSU. State machines, digital systems, VHDL, intro to test.
2. ECE 572. Advanced Logic Synthesis. Introductory graduate class. Logic synthesis theory, decomposition, multi-valued logic, Reed-Muller and Galois circuits.
3. ECE 510DT. Test and Design for Test.
4. ECE 478. Intelligent Robotics 1.

LECTURE 1.

FUNDAMENTALS OF VHDL AND PROJECTS.

MANDATORY MATERIAL

1. Class organization. Projects. Grading. Exams.
2. REVIEW: Flip-Flops. Shifts. Generalized Registers. Register Transfer and Kmaps.
3. Introduction to VHDL. Design styles. Behavioral, functional and structural descriptions.
4. Objects, Types and Operations.
5. SLIDES: Lecture 1, about class and review.
6. Short discussion of class projects for this quarter, and creation of project groups.

INTRODUCTORY HOMEWORK.

1. This is just to create your WWW Page for this class. It does not qualify as one of two "official" homeworks (mini-projects) for this class.
   
   Create your own WWW Page for this class.
2. Write about your interests in VHDL, digital design, design automation, ASIC design, computer architecture and related topics.
   
   Add links to the pages of your interest from the WWW.

PROJECT.

LECTURE 2.

MANDATORY MATERIAL

1. Register Transfer description.
2. SLIDES: Lecture 2. Diagrams and VHDL Intro. Examples of various description types in VHDL.
3. Continuation on basic hardware description concepts. Examples of descriptions of simple machines and logic and sequential blocks.

EXAMPLE OF GOOD HOMEWORK REPORT

1. PDF File: Example of good homework 1 design and documentation. Robot Arm.

TOOL USE DESCRIPTION. ONLY IF YOU NEED IT.

1. PDF File: Modeling Tool Use How to use Modelsim tools.
2. SLIDES: Mentor Graphics Tools. How to use Mentor tools.

ADDITIONAL READING AND REVIEW. ONLY IF YOU NEED THEORY REVIEW ON STATE MACHINES.

1. Review Kohavi's textbook on basic material and state machines.
2. You can use also Mano/Kime, Roth or Wakerly texbooks.

OFFICIAL HOMEWORK NUMBER ONE.

• from my WWW page,
• from any book on VHDL,
• as a part of your final project,
• presented or mentioned in VHDL class,
• or any problem in VHDL of your interest.

It should be a large combinational circuit with hierarchy, a state machine, a data path or a controller composed of a controlling state machine and data path controlled by it. This homework should be simple but not trivial and should be done by a single person, not a group. However, working on homeworks and projects in groups and learning EDA tools together is highly recommended. Just the final work of writing code and testing it is an individual assignment. In projects you will work together on everything.

LECTURE 3.

SEQUENTIAL STATEMENTS AND FINITE STATE MACHINES.

MANDATORY MATERIAL

1. Sequential statements.
2. Structural modeling.
3. Data Flow modeling.
4. Finite State Machines.
5. SLIDES: Timing and Simulation

ADDITIONAL SLIDES, ONLY FOR PROJECTS. REVERSIBLE LOGIC.

1. SLIDES: Lecture 3 of Kerntopf about reversible logic fundamentals.

ADDITIONAL READING AND MATERIALS

1. Complete reading in Kohavi about FSMs, and if necessary, previous chapter(s).
2. You can use also Mano/Kime, Roth or Wakerly texbooks. I found Roth and Mano/Kime particularly useful for beginners.

LECTURE 4.

DESIGN OF COMPLETE REGISTER TRANSFER LEVEL CONTROLLERS IN VHDL.

MANDATORY MATERIAL

1. Data flow modeling.
2. Complete descriptions of Finite State Machines.

USE OF TOOLS.

1. SLIDES: Modelsim Tools Advise

EXAMPLES OF GOOD HOMEWORKS.

1. SLIDES: Robot Design. Example of a complete state machine

ADDITIONAL SLIDES. PROJECT RELATED ONLY. CUBE CALCULUS MACHINE.

1. SLIDES: Cube Calculus
2. SLIDES: Cube Calculus Machine Architecture Fundamentals This is an architecture that has a one-dimensional, two-directional network of FSMs.

ADDITIONAL SLIDES. PROJECT RELATED ONLY. EVOLVABLE HARDWARE.

1. SLIDES: Learnining Hardware and Evolvable Hardware

LECTURE 5.

DESIGN OF FINITE STATE MACHINES IN VHDL.

MANDATORY MATERIAL

1. Design of an adding counter using D or T ffs. Iterative design versus design based on Kmaps.

ADDITIONAL READING

1. Read Kohavi about structural design of FSMs. You can use also Mano/Kime, Roth or Wakerly texbooks.

MANDATORY MATERIAL

1. Characteristics of iterative and sequential circuits:
   1. one-dimensional, one directional, combinational. Standard Iterative circuits.
   2. one-dimensional, two directional, combinational. Iterative circuits composed from two iterative circuits with different directions.
   3. two-dimensional, one and two directional, combinational. Number of neighbors = 2,3,4,5, 6.
   4. one-dimensional, sequential.
   5. two-dimensional, sequential.
2. Combinational Circuits in VHDL

ADDITIONAL MATERIAL

1. Read chapter about combinational descriptions in VHDL from your textbook. To review combinational logic, you can use also Mano/Kime, Roth or Wakerly texbooks.

LECTURE 6.

ASSIGNMENT STATEMENTS. CONDITIONALS.

1. HOMEWORK ONE IS DUE TODAY
2. Assignment Statements
3. Conditionals
4. SLIDES: Data Flow Modeling.

MANDATORY MATERIAL

1. Structural modeling.
2. Review on logic blocks.

1. Review on CAE tools and basic technologies in which FSMs are realized.
2. SLIDES: Structural Modeling II.
3. SLIDES: Modern Tools for VLSI.
4. SLIDES: Design Methodologies in VLSI.

LECTURE 7.

MANDATORY SLIDES. NEW MATRIAL AND REVIEW.

1. SLIDES: Homework 1. Student solution.
   
   
2. SLIDES: lecture001-intro.ppt
   
   
3. SLIDES: lecture002-diagrams-vhdl-intro.ppt
   
   
4. SLIDES: lecture003-FSMs.ppt
   
   
5. SLIDES: lecture004-reversible-logic.ppt
   
   
6. SLIDES: lecture005-FSM2-GENERATE statement.ppt
   
   

AUXILIARY SLIDES. NEW MATRIAL AND REVIEW.

1. SLIDES: lecture007-Mentor-Graphics-Tools.ppt
   
   
2. SLIDES: lecture008-Modelsim-Tools-Advise.ppt
   
   
3. SLIDES: lecture009-combinational-circuits.ppt
   
   

MANDATORY LECTURES ON SIMULATION AND TIMING IN VHDL.

1. SLIDES: lecture010-timing-and-simulation.ppt
   
   
2. SLIDES: Lecture011-Advanced-use-of-signals.ppt
   
   

AUXILIARY LECTURES ON SIMULATION AND TIMING IN VHDL.

1. SLIDES: Lecture012-Signal-Attributes.ppt
   
   
2. SLIDES: Lecture014.Discrete_event_simulation.ppt
   
   
3. SLIDES: lecture016.Objects_types-operations.ppt
   
   

LECTURES 8, 9 and 10.

ADVANCED MATERIALS.

1. REMINDER: HOMEWORK 2. This homework must include Finite State machine as its part and must have synthesis with discussion of variants. Otherwise you are free to select any topic of your interest. Use Leonardo or similar toold. Map to an FPGA.
2. Combinational circuits in VHDL.
3. Assignment statements.
4. Technology review.

1. Object types and operations
2. CPLDs and FPGAs for our projects
3. DSP Circuits
4. Review on logic and sequential blocks. Use of logic blocks in sequential machines.
5. Shifters, counters.
6. SLIDES: Multiplexers, Decoders, ROMs. Use in design.
7. SLIDES: PAL, PLA, EPLD, FPGA. Complex PLD (CPLD).
8. SLIDES: Arithmetic Circuits. Full adder. Adder/Subtractor. Ripple Carry Chain. Carry Look-Ahead adder. Carry Select Adder. Generalization of these Principles.
9. SLIDES: Arithmetic Circuits. Serial Adder. ALU, Parity. Comparators. Multiplier.
10. SLIDES: Combinational circuits in VHDL.
11. SLIDES: Assignment statements.
12. SLIDES: Technology.

1. Conditionals.
2. Basic Timing Model and simulation.
3. Modeling Tools Use. How to use our tools. Very useful guidelines.

1. SLIDES: Conditionals.
2. SLIDES: Basic Timing Model and simulation.
3. SLIDES: Modeling Tools Use.

1. Data Types.
2. Modeling Constructs.

1. SLIDES: Data Types.
2. SLIDES: Modeling Constructs.

1. Procedures and functions.
2. Test Benches.
3. Overview of synthesis and synthesis tools.

1. SLIDES: Procedures and Functions.
2. SLIDES: Test Benches.
3. SLIDES: Synthesis tools.

LECTURES 11, 12, 13, 14, 15 and 16.

LOGIC DESIGN OF SYSTOLIC PROCESSOR AND CELLULAR AUTOMATA.

1. Systolic Processors.
2. Advanced and Reconfigurable Systolic Processors.
3. DNA matching systolic architectures.
4. Reconfigurable Pipelines.
5. Very Long Instruction Word (VLIW) Architectures.
6. Example of good student project. Software, hardware, VHDL. Use of parallel concepts from the class in project. Jacob Boles.
7. Design of a Intel microcontroller in Xilinx.
8. Design of a complete ASIC CPU.
9. Introduction to EDA tools. Or, what is inside your VHDL-based tools.

COMPUTER ARCHITECTURES AND THEIR VHDL DESCRIPTIONS.

1. Systematic Designing of a microprocessor after Mano and Kime
2. Basic Pipelining Techniques
3. Basic Clocking Schemes Design
4. Introduction to Parallel Computing and Processors
5. Parallel Machine Classification
6. Cellular Automata.

MANDATORY SLIDES. LECTURES ON SYSTOLIC PROCESSORS, PARALLEL PROCESSORS, FPGA ARCHITECTURES AND SIMILAR TOPICS.

1. SLIDES: SY_lecture006.-introduction-systolic.ppt This is an introductory lecture on systolic architectures. Definitions of systolic computing and systolic arrays. Typical structures. Systolic computers have both pipelining and parallelism. SIMD vs Systolic. Host Station in Systolic. Variations of systolic architectures. 1-Dimensional and 2-Dimensional Arrays. Focal Plane with 3-Dimensional Input-output. Hexagonal arrays. Hypercubes. Trees. Lattices. Applications. Characteristics of Systolic Arrays. Advantages of Systolic Arrays. Using VLSI effectively. Eliminating Von Neuman's Bottleneck. Balancing I/O and computation. Exploiting Concurrency.
   
   
2. SLIDES: SY_lecture007.-systolic-one-dimensional.ppt Examples of One-Dimensional Systolic Arrays. Motivation and Introduction. Pipelined Computations. Sieve of Eratosthenes. Systolic Arrays from Intel. Systolic Algorithms. Pipelined Polynomial Evaluation. Matrix Vector Multiplication. Systolic Processors versus Cellular Automata versus Regular Networks of Automata. Convolution Circuits Synthesis. FIR-like filter structures. Optimization based on tranformations. FIR Filter or Convolver design. Bag of tricks to be used. Bogus attempts. Types of circuits for convolution. Remarks on designs. FIR filter design. Large Systolic Arrays as general purpose computers. Problems with systolic array design. Key architectural issues. Two-Dimensional Systolic Arrays.
   
   
3. SLIDES: SY_lecture008-two-dimensional-systolic.ppt Obvious matrix multiplication. Systolic matrix multiplication. Examples. Visualization (animation). Data Flow. Programming issues.
   
   
4. SLIDES: SY_lecture009-systolic-two-dimensional-begin.ppt Applications of Systolic Arrays. Hexagonal array for matrix multiplication. Systolic array multiplier of numbers. Triangular systems for solving equations and similar problems. Systolic Organization for future nano-technologies. Organization. Future circuits. Principle of Local Communication. New Concept in Computer Architecture. Systolic Characteristics. Systolic different than pipelined. Systolic Different than Array Processors. Automatic Design of systolic processors. Integration. Systolic Issues.
   
   
5. SLIDES: SY_lecture012-advanced.ppt Systems for real-time systems. Comparison of types of systolic and similar architectures. 3D systolic architectures. Radar Processing as an example. Evaluation of Scorecard. Baseline Parallel Architecture. Complex Butterfly. Efficient Complex Multiply. Parallel-Pipelined Architecture. Serial Input. Serial Architecture. High Level View. 8192-Point Architecture. Increase Parallelism. Simplification. Results. Typical applications. Least Square Algorithms. Matrix Inversion. Internal Cells. Other applications. Drawbacks. Wave-Front Architecture.
   
   
6. SLIDES: SY_lecture015.Cellular-Automata.ppt What are cellular automata. Example of two-dimensional automaton. The specifications of cellular automata. What is the main characteristics of Cellular Automata. What are the Applications of Cellular Automata ? Examples of Applications of CA. One-Dimensional CA with Wrap-Around. LIFE the game. Life Patterns. Cells of CA. Interaction. Neighborhood. States. 3D automata. Cellular Automaton for Voting. Examples of applications. Consumer-Resource interactions. Predator-Prey. Classification of CA. Types of CA. Wolfram. Complexity. Universal Machines. Self-Reproduction. Games. Life and complexity. Rules of Life. Emergent Behavior. Cellular Automata and Emergence. Analysis of Emergence. Other Systems of Artificial Life that may be modeled on CAs.
   
   

NEW 2008 AUXILIARY SLIDES: ADVANCED 2D PROCESSOR DESIGN.

1. SLIDES: SY_lecture010-Advanced-two-dimensional-systolic.ppt Examples of two-dimensional Systolic Arrays. Cannon method as an improvement of standard architecture. Applications of Cannon's Method. Partitioned Multiplication. Block Multiplication. Exercise. Fox's Algorithm. Synchronous Computations. Barriers. Counter Method for Barriers. Tree Barrier. Butterfly Barrier. Barrier Bonuses. Data Parallel Computations. FORALL synchronization assumptions. EXAMPLE: Prefix-Sum. Implementing FORALL using SPMD. Example: Iterative Linear Equation Solver. Nested FORALLs. EXAMPLE: Laplace Heat Equation. Exercise. Synchronous Computations. Barrier Synchronizations. Common Parallel Programming Paradigms. Synchronous Computations. Example: Bitonic Sort. Bitonic Sort Algorithm. Shuffle-Exchange. Bitonic Sort on Hypercube. Mappings of Bitonic Sort. Stone's algorithm. Many-one Mappings of Bitonic Sort. Compare-Split. Performance Issues. Conclusion on Systolic Arrays. Disadvantages of Systolic Arrays. Parallel Overhead.
   
   
2. SLIDES: SY_lecture011-pattern-matching-systolic.ppt Pattern Matching. Character Matching. Visualization. Join Operation. Systolic organization for Join.
   
   
3. SLIDES: SY_lecture019.Signal-Processing-circuits.ppt
   
   

PREVIOUS AUXILIARY SLIDES: EDA TOOLS AND PROCESSOR DESIGN.

1. SLIDES: Introduction to EDA tools.
2. SLIDES: Microprocessor design. Mano and Kime
3. SLIDES: Pipelining
4. SLIDES: Clocking

AUXILIARY SLIDES: DESIGNING ADVANCED PARALLEL ARCHITECTURES. FPGA DESIGN.

1. SLIDES: Parallel Computing
2. SLIDES: Design of a Intel microcontroller in Xilinx.
3. SLIDES: Machine Classification
4. SLIDES: Cellular Automata.
5. SLIDES: Systolic Processors.
6. SLIDES: Advanced and Reconfigurable Systolic Processors.
7. SLIDES: DNA matching systolic architectures
8. SLIDES: Reconfigurable Pipelines

AUXILIARY SLIDES: DESIGNING MODERN NON-STANDARD ARCHITECTURES.

1. SLIDES: VLIW Architectures
2. SLIDES: Satisfiability machine of Boles.
3. SLIDES: Design of a complete ASIC CPU.

LECTURE 17. MONDAY, May 19, 2008.

MANDATORY SLIDES: TESTBENCHES.

1. SLIDES: TEST00_Enumerated_types_testbeds.ppt Asheden. Types. Resolution functions and Testbeds. Simple testbed example. Types. Objects. Standard Types and std_logic types. Operators available. Bit and Boolean. Integer types. User defined types. Examples of strong typing. Integer types, synthesis. Integer types, Example. Enumerated types. Multi-valued Logic types. std_logic. Arrays. Array example. Attributes: Integer and Enumeration Types. Attributes: Arrays. LED Decoder, Using Arrays. std_logic Resolution Function. Two Examples. Records. Stack Testbench. Delayed attribute. Fuzzy Logic Homework Assignment. Fuzzy Logic Testbench.
   
   
2. SLIDES: TEST01_Encapsulation_Testbench.ppt Configuration. Test Bench. Encapsulation. Structural Decomposition.
   
   
3. SLIDES: TEST03_large-scale-design.ppt Managing Design Complexity. Partition of designs. Typical design process using VHDL. Test Bed. A VHDL example.
   
   

AUXILIARY SLIDES: GALOIS FIELD ARITHMETICS.

1. SLIDES: GF-2n-LOgic-Tenca.ppt Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2^n). Motivation and related work. GF(p) Montgomery inverse algorithm and hardware. GF(2^n) Montgomery inverse algorithm. The unified and scalable architecture implementation. Area and speed comparisons.
   
   

LECTURE 18. WEDNESDAY, MAY 21, 2008.

MANDATORY SLIDES: BEHAVIORAL.

1. SLIDES: BEH_001_behavioral-statements.ppt Signals. Drivers. Multiple Drivers. Resolution. Sequential Control Statements. Behavioral Description in VHDL. Modeling Combinational and Sequential Logic. D-Latch Example with Set-up and hold checks. Modeling FSMs. Mixed Descriptions in VHDL. IF statements. If statement timing. SELECT. CASE. Choices. Examples. Null statement. LOOP statement. Inner and outer loops. While Loops. For Loops. NEXT statement. EXIT statement. Assertion Statements. Report Statement. Aliases.
   
   
2. SLIDES: BEH_002_procedures-and-functions.ppt Subprograms. Functions. Procedures. Signal Resolution. Bus resolution. Null transactions. Concurrent statements. Concurrent Signal Assignment. Concurrent Signal Sensitivity. Conditional Signal Statement. Selected Signal Statement. Concurrent Procedure Call. Concurrent vs Sequential Statements in Simulation cycles. Blocks. Nested Blocks. Modeling styles. Behavioral modeling. Data Flow model. Signal Assignment Statements.
   
   
3. SLIDES: BEH_005_Resolved-signals-GUARDS.ppt Blocks, Resolved Signals, Signal Guards, Tri-State Buses.
   
   

LECTURE 19. MONDAY, MAY 26.

LECTURE 20. WEDNESDAY, May 28, 2008.

MANDATORY SLIDES: SYNTHESIS.

1. SLIDES: lecture_SYN_021.high-level-synthesis.ppt Tasks of Designer/Manager. The Henry Ford Assembly line. Aspects of Pipelining. A Werner Diagram Pipeline. A view of the synthesis and design. Gajski's Y-Chart. Parameters of Design. Floorplanning. Fighting Complexity. Example. Partial Differential Equation. Numerical Solution in C. Examples of scheduling and allocation. Earliest Deadline (ASAP). Hardware Solution number 2. Hardware solution number 3. Latest deadline ALAP. Time Constraints with ILP. Resource constraints with Lists. Harmony and balance in Design. Raytracing. Long Convolutions. Kung Systolic array. Spatial Computing. Steps to design. Problems for students to solve.
   
   
2. SLIDES: lecture_SYN_023.SIS-and-logic-synthesis.ppt CAD algorithms and tools. Multi-level logic synthesis. SIS as a representative CAD tool. Boolean Networks. Transformations of Boolean Networks. Optimization loop. Implementation. Network/node data structure, packages, scripts. Conclusions.
   
   
3. SLIDES: lecture_SYN_024.CPLD-FPGA.ppt Programmable Chips and Boards. Implementation technologies. Full Custom and Gate Arrays. PLD, EPLD, CPLD. FPGA. Xilinx XC6200.
   
   
4. SLIDES: lecture_SYS_026-combinational-blocks.ppt Useful Combinational Basic Blocks in VHDL. Decoders. Decoders in VHDL. 3 to 8 Decoder in VHDL. 7-segment decoder. Encoders. Multiplexers. Multiplexer with one control. Behavioral Synthesis of sequential selection instruction. Behavioral Synthesis of sequential selection instruction using CASE. Synthesis of numeric types: Integer and Real. Synthesis of Enumerative Types. Type: STD_LOGIC_1164. Synthesis of assignment statements for logic operators. Synthesis of assignment statements for relational operators. Synthesis of arithmetic operators. Synthesis of logic copying instructions. First example of synthesis of "Logic copying instructions". Second example of synthesis of "Logic copying instructions". XOR and Parity Circuits. Comparators. Adders, Subtractors and ALUs. Adder with Argument Selection. Adder and its circuit generated from cells. Another Adder. Arithmetic Circuits. Multipliers. ROM Implementations.
   
   
5. SLIDES: lecture_SYS_027-synthesis-sequential.ppt VHDL and Sequential Circuit Synthesis. Multiple architecture for the same entity. What is synthesis. Advanced Data Flow Diagram. Watch Out for these statements. Basic Sequential Elements. Descriptions using latches. Modeling latches. Description using Edge Triggered Flip-Flops. Description using Edge Triggered Flip-Flops with complex excitation function. Description of synchronous SET/RESET Flip-Flops. Synchronous SET/RESET Flip-Flops. Asynchronous SET/RESET Flip-Flops. Clock Enable Flip-Flops. Flip-Flops inferred by Wait Until. Avoid undesired memory elements. Flip-Flops inferred by variables. Edge Synchronization using Function RISING_EDGE. Description of Tristate Buffers. Description of wired circuit using Tristate Buffers. Flip-Flops with Tristate Buffers. Tristate Buffer at the FF's output. Busses with Tri-state buffers. Three-State Multiple-Drivers. State Machines. Two-Process FSM. Example: Two-Process FSM. Combinational Logic. VHDL Tri-State Bus. VHDL register. State Machines. Examples. Implementation of PULSE_GEN. Modeling FSM. Mealy and Moore automata. Recommended type of FSM modeling. Output Synchronization of State Machines. Counters. CAUTION: Hardware realization of VHDL objects. State Encoding. Illegal States. Dealing with State Machines. Example Machine. State Diagram. Next State Decoding. Decoding States for output signals. RESET circuits. Dealing with illegal states. "Safe State Machines". Exam Material: Architecture review. Anatomy of CSA. Processes. Process examples. Variables. Signals. Latching. Latch inference. Microprocessor I/O Ports. Looping to replicate Hardware. Range Attributes. For Loop. Exit Statement. While Loop Syntax. WAIT statement. Some Synthesis limitations. Registers. D-Flop variants. Synchronous Design. Typical Synchronous System. Synchronous System Issues. Clock Skew. Global Clock Buffers. Input Synchronization. Simple examples; Counters and timing.
   
   
6. SLIDES: lecture_SYS_028-FGA-synthesis.ppt Advanced techniques in design optimization. Introduction to synthesis tools. Design Flow using FPGAs and ASIC. Optimization of a counter. Advanced: think in hardware. Commercial Synthesis tools. Leonardo Spectrum. FPGA express. Completing design flow in FPGAs. Advantages in Synthesis to PLDs and FPGAs. Disadvantages in Synthesis. Other approaches.

EXAMPLES OF PAST HOMEWORKS AND PROJECTS.

1. SLIDES: AlanFryer=Pacemaker.doc
   
   
2. SLIDES: HW1-Reversible-Adder.doc
   
   
3. SLIDES: KelleyECE590hw1.pdf
   
   
4. SLIDES: KelleyECE590hw2.pdf
   
   
5. SLIDES: PE013.DEC-PERLE-BOARD.PPT
   
   
6. SLIDES: Reversible-Adder-VHDL.pdf
   
   
7. SLIDES: SchmidlKoferProjectECE590.doc
   
   
8. SLIDES: andrzej_janczak-hw1.doc
   
   
9. SLIDES: bista-HOMEWORKI.doc
   
   
10. SLIDES: bista-HOMEWORKII.doc
    
    
11. SLIDES: bista-Hough_Cordic.pdf
    
    
12. SLIDES: Bista-place-and-route-report.doc
    
    
13. SLIDES: Bista-synth-report.doc
    
    
14. SLIDES: Bista_static-timing-report.doc
    
    
15. SLIDES: bita-map-report.doc
    
    
16. SLIDES: HughesPolarityOptimizer.doc
    
    
17. SLIDES: Hughes-Comparator.pdf
    
    
18. SLIDES: Hughes-Hough-Transform.doc
    
    
19. SLIDES: hughes-timing-diagram.doc
    
    
20. SLIDES: derek-hw2-beverage serving-robot.doc
    
    
21. SLIDES: sunardi-hm1.doc Braitenberg Vehicle Robot.
    
    
22. SLIDES: sunardi-hm2.doc Motion generation for a robot.
    
    

LECTURE 21. MONDAY, JUNE 2, 2008.

TO DISCUSS.

1. Packages and aliases.
2. Processor design.
3. System Level Modeling.
4. Packages and Aliases.

MANDATORY SLIDES: STRUCTURAL MODELING.

1. SLIDES: lecture023-structural-modeling.ppt Structural Modeling. Entities. Ports. Architectures. Packages.
   
   
2. SLIDES: lecture027-package-modeling-mvl.ppt Packages. USE Clause. Aliases. Data Alias. Non-Data Alias. Resolved Signals.
   
   
3. SLIDES: lecture_SYN_020-synthesis-from-VHDL.ppt Synthesis from VHDL. Design entry. Add-on tools. Synthesis. Layout Synthesis. Example of VHDL code for layout synthesis. VHDL-to-STD-cell. Logic Synthesis. Timing Optimization. Combined timing-size optimization. Problems in synthesis. Wire loading. RTL vs High-Level Synthesis. Synthesis from VHDL. FSM specification for synthesis. RTL synthesis for VHDL: An Example. HLS synthesis for VHDL. Signal assignment semantics. Estimate using floor plan. Vertical Synthesis. VHDL versus Verilog in Synthesis. Compiled vs Interpreted. Synthesis in the future. Problems for students to solve.
   
   
4. SLIDES: Packages and aliases. Packages, Package Declaration. Package Declaration Syntax. Package Declaration Example. Package Body. Package Body Syntax. Package Body Example. Library clause. Use Clause. Use Clause Syntax. Use Clause Example. Aliases. Data Alias Syntax. Data Alias. Non-Data Alias Syntax. Resolved Signals. Resolved Signal Syntax. Resolved Signal Example.
   
   
5. SLIDES: System Level Modeling. System level modeling in RASSP Roadmap. Module goals. Requirements for Effective System-level modeling. System level modeling definitions. Abstraction. Levels of Abstraction. Executable Specifications. Executable Specifications: MIT Lincoln Laboratories. Express VHDL/i-Logic. Performance Modeling Overview. Performance Evaluation. Uninterpreted Models. Petri Nets. Queuing Models. Token-Based Simulation Models. ADEPT. Honeywell Performance Modeling Library. Interpreted models. Hybrid Models. ADEPT hybrid modeling. Object-Oriented Analysis. Advantages of OO analysis. Dependability Outline. Errors and Faults. Dependability Modeling Definitions. Need for Dependability Modeling. Additional Metrics. Analytical Techniques. Combinatorial Models. Semi_Markov Unreliability Range Evaluator (SURE). Simulation-Based Techniques. Reliability Estimation System Testbed (REST). Functional Modeling. Functional Modeling in MATLAB. MAT2DSP. Ptolemy. Ptolemy Capabilities. Bus Functional Models. Example. Bus Functional Example - Alchemist.
   
   
6. SLIDES: DP32 Processor. Case Studies: DP-32 Processor. From Asheden's VHDL Cookbook. Complete Word Format Document on Web. Behavroral description. Structural Description in form of RTL. Entity, Architecture, Configuration, Packages, etc. DP 32 registers. Arithmetic Instructions. Typical 32-bit Instruction format. Port Diagram. Two-phase, non-overlapping clock. Bus Read timing. DP32 Package. Package Body. DP32 entity. DP32 Architecture. DP32 Behavioral Architecture. DP32 Behavioral Subtract. DP32 Behavioral Kernel - Reset. DP32 Behavioral Kernel. DP32 Behavioral Partial Decode. DP32 Test Bench. DP32 Test Bench Entity. DP32 Test Bench Architecture. DP32 Memory Entity. DP32 Memory Architecture. Successive Approximation A/D. S/A algorithm. Assuming 8-bit conversion. Approximations. Negative-Valued Inputs.
   
   
7. SLIDES: DP Processor Components. Case Study Components. DP-32 Processor, RTL. RTL Implementation of DP-32. Components needed. Default. 2-input MUX. Transparent Latch. Buffer. Sign-Extending buffer. Latching Buffer. Program Counter Register. Register File. ALU. Condition Code Comparator. Controller. RTL Testbench.

LECTURE 22. WEDNESDAY, JUNE 4, 2008.

TO DISCUSS.

1. Structural Overloading.
2. Bus resolution, more examples.
3. Arrays.
4. If time will allow, show more examples of test-benches.

MANDATORY SLIDES.

1. SLIDES: BEH_006_Structural_Overloading.ppt Structural Model. Procedures. Functions. Overloading.
   
   
2. SLIDES: BEH_007_bus-resolution-sorter-multiplier.ppt Behavioral VHDL. Testbenches. Signal Assignment Statements. Inertial vs Transport Delay. Entity statements. Blocks and guards. VHDL packages. Potential Problems to avoid. Resolving Difficulties. Three examples of Behavioral Description. Package with Bus Resolution Function. Unsigned 8 bit Multiplier Controller. Package for Quicksort Routine.
   
   
3. SLIDES: BEH_008_examples_ROM.ppt Why behavioral. Wait Statement. Signal Timing. Examples of behavioral descriptions: ROM.
   
   
4. SLIDES: BEH_011_arrays.ppt Data Types. Composite Data Types. Arrays. Records. Constrained vs unconstrained arrays. Two Examples of Predefined Unconstrained Types. Unconstrained Array Ports. AND example. Array reference. Examples of Array Aggregate. Examples of Named Association in Array Aggregate. Array Operations: element by element logic operations. NOT operations. 1D Shift and Rotate Array Operations. Shift and Rotate Operations. Relational Array Operations. Array Operations: Concatenation. Conversion from one Array Type to Another. Example of Array Type Conversion. Example of Array Aggregate. Predefined Attributes. Array Type Bound Example: use of predefined attributes. Another example of array bound. Multi-range array attributes. Array length attributes. Range attributes. Type attributes position function. Homework: Attributes exercise. Example of using Attributes. User Defined Attributes. Records. Examples of records.
   
   
5. SLIDES: BEH_012_files-access-type.ppt VHDL advanced Features. Buses. Access Type. File Input/Output.
   
   
6. SLIDES: lecure02_advanced-Basic-Structura-lVHDL.ppt Entity Declarations. Port Clause. Component Declaration. Configuration Declaration. Architecture Bodies. Signal Declarations. Wait Statement. Sensitivity Clause. Concurrent Assertions. Passive Statements.
   
   
7. SLIDES: vhdl2pld.ppt Specifying Programmable Logic. JEDEC files. JEDEC Formats. PLD Programming Options. Creating a JEDEC file. PLD Programming Language. PLD Programming. Boolean Equations in VHDL. Operator Precedence. A Complete VHDL Model. Comments on Example. How Much VHDL do YOU have to know? Using Internal Signals. VHDL Template for SSN Decode (Entity). VHDL Template for SSN Decode (Architecture). Compiling, Simulating, JEDEC File Creation. Compilation/Simulation Results. Compilation/Simulation Failure.
   
   

LECTURE 23. JUNE 9, 2008. WEEK OF FINALS.

TO DISCUSS.

1. Verilog for state machines.
2. Verilog for combinational circuits.
3. Verilog for testbenches.
4. Behavioral descriptions in Verilog.

MANDATORY SLIDES: VERILOG.

1. SLIDES PDF: Verilog Lecture in PDF

AUXILIARY SLIDES: VERILOG.

1. SLIDES: 001.verilog-intro.ppt
   
   
2. SLIDES: 002.ch5_verilog.ppt
   
   
3. SLIDES: 005-fpga-Spartan-verilog-2003.ppt
   
   
4. SLIDES: CHAPTER-8.ppt
   
   
5. SLIDES: PLI-intro.ppt
   
   
6. SLIDES: FinalProjectPresentation-Fareena3.ppt

AUXILIARY SLIDES: CODING STANDARDS IN VHDL.

1. SLIDES: ESA Coding Standards." ESA Modeling guidelines. Basic Language. Readability Standards. Naming Conventions. Comments. Required File Header. Subprogram description. Port and Generic Clauses. Types. Literals. Files. Signals. Ports. Assertion Statements. Assertion Severity Levels. Declarations. Configurations. Packages. Design Libraries. Constructs to Avoid. Verification. Deliverables. Specific Model Requirements. Component Simulation Model. Allowed Types. Component Model Interface. Component Model Signals. Board Level Simulation Models. Board Level Model Interface. Board Level Simulation Models. Board Level Model Timing. Board Level Timing Parameters. Board Level Verification. System Level Simulation.
   
   
2. SLIDES: Discrete Events Simulation. Discrete Event Simulation (DES) and VHDL. DES Properties. Why Discuss DES. Two Approaches to DES. Queues. Efficient Simulator. Internal Event Queues. Simulation Determinism. Stochastic Simulation. System Stressing. Simulation Validation. Concurrent Simulation. VHDL Implementation of FSMs. FSM Types. FSM Equivalence. DFA/NDFA. Inappropriate Use of FSMs.
   
   

LECTURE 24. JUNE 11, 2008. WEEK OF FINALS.

MANDATORY SLIDES ABOUT VERILOG.

1. SLIDES POWERPOINT: Verilog Lecture in PPT Verilog Language. Structural Modeling. Behavioral Modeling. How Verilog is used. Two Main Components of Verilog. Two Main Data Types. Discrete-Event Simulation. Four-Valued Data. Four-Valued Logic. Structural Modeling. Nets and Registers. Modules and Instances. Instantiating a Module. Gate-Level Primitives. Delays on Primitive Instances. User-Defined Primitives. A Carry Primitive. A Sequential Primitive. Continuous Assignment. Behavioral Modeling. Initial and Always Blocks. Procedural Assignment. Imperative Statements. For Loops. While Loops. Modeling a FLIP-FLOP With Always. Blocking vs Non-Blocking. A Flawed Shift Register. Non-Blocking Assignments. Non-Blocking Can Behave oddly. Non-blocking Looks Like Latches. Building Behavioral Models. Modeling FSM Behaviorally. FSM with Combinational Logic. FSM from Combinational Logic. FSM from a Single Always Blocks. Simulating VERILOG. How are simulator used. Writing Testbenches. Simulation behavior. Two Types of events. Simulation behavior. Verilog and Logic Synthesis. Translating VERILOG into Gates. What can be translated. What isn't translated? Register Inference. Inferring Latches with Reset. Simulation-Synthesis Mismatches. Compared to VHDL.

FINAL PRESENTATIONS OF STUDENT PROJECTS.

1. I recommend that you present your oral lecture about your project for me when I will be back. If you cannot do this after June 21, please record it or present it in the class.
2. They will be videotaper and I will to view all these presentations when I will be back.
3. I will also talk to Martin about his impressions.
4. Future links to student www pages with projects.
5. Future links to student www pages with projects.
6. Please send me links to your projects.

You can reach me at
mperkows@ee.pdx.edu