Scalable Co-Verification Based on Hardware IPs and Software Component

Executive Statement

The goal of this project is to develop a component-based approach to scalable hardware and software co-verification of embedded systems using model checking, which unifies the concepts of hardware IPs and software components, leverages advances in assertion-based verification, extends effectiveness of compositional model checking for system-level co-verification, and facilitates verification reuse.

Project Members

Past Members


Software Packages

In this project, we have developed an Embedded System Integrated Development Environment (ESIDE). Embedded system development using ESIDE starts with selecting a platform for embedded systems which provides the platform-specific libraries for architectural patterns and reusable components. Component-based co-design generates the  architectural specifications of the system and its components, which are utilized in both component-based co-simulation and co-verification together with the platform-specific libraries. The validated and verified designs are compiled to deployment images for both hardware and software by the component-based co-synthesis. There are feedback loops from co-simulation, co-verification, and co-synthesis back to co-design for reporting design errors detected.

The co-design and co-verification tools from ESIDE are currently available for download here.

Conference Publications

Journal Publications

Related Publications from Previous Projects