READING ASSIGNMENT

1. Read chapter 4 from Wakerly in full detail. Solve as many problems as necessary to become fluent using Kmaps and expressions.

   MANDATORY SLIDES

   1. PDF. n4.prn.pdf. Boolean Algebra and Logic Operations. Fundamentals.
   2. PDF. L007.prn.pdf. Realization of Digital Circuits. Logic Circuits, Truth Tables, K-Maps, and ROMs.
   3. PDF. L008.prn.pdf. Minimization of Combinational Logic Using K-Maps. Fundamentals.
   4. PDF. L010.prn.pdf. Multiple-Output SOP (Sum of Products) minimization. This lecture teaches you how to use Kmaps to solve multi-output functions.

   ADDITIONAL SLIDES

   1. PDF. L009.prn.pdf. Additional Reading Material about Combinational Circuit and Combinational Optimization and Decision Problems. Set Covering, Petrick Function, Maximum Clique and Graph Coloring. Unate and Binate Covering. These are advanced methods to solve covering tables. We use them also in test minimization.

Material to be covered in Quizzes and First Midterm.

1. Review of Karnaugh Maps: variables, literals, products, product implicants, Prime implicants, essential prime implicants.
2. How to draw a Kmap.
3. Finding good groups in a Kmap.
4. Covering problem.
5. Mathematical Method to solve the covering problem: Petrick function.
6. Various uses of Kmaps to design with Muxes.
7. Analysis methods (based on Kmaps, netlists, expressions).
8. The importance of good selection of the analysis method.
9. The relations between analysis and synthesis.
10. NAND and NOR gates. Their use.
11. Latches - review.
12. Flip-Flops - review.
13. Synchronous Devices.
14. Designing binary counters.
15. Designing sequential parity checkers.
16. Please look to data sheets at the bottom of this page for practical examples of logic and sequential blocks, components, counters, etc.
17. Read about sequential parity checkers.
18. The notations used for state machines.
19. Moore and Mealy machines, examples.
20. Review of the basic method to calculate the excitation functions for Mealy machines.
21. Timing analysis of Mealy machine.
22. Review of Shifters.
23. Analysis of autonomous FSM.
24. Analysis of non-autonomous FSM: from schematic to state machine graph.

LECTURES 2 and 3:

BASIC FLIP-FLOPS AND SIMPLE SYNCHRONOUS CIRCUITS.

CONCEPTS TO BE COVERED.

1. Various uses of Kmaps to design with Muxes.
2. Analysis methods (based on Kmaps, netlists, expressions).
3. The importance of good selection of the analysis method.
4. The relations between analysis and synthesis.
5. NAND and NOR gates. Their use.
6. Latches - review.
7. Flip-Flops - review.
8. Synchronous Devices.
9. Designing binary counters.
10. Designing sequential parity checkers.
11. Please look to data sheets at the bottom of this page for practical examples of logic and sequential blocks, components, counters, etc.
12. Review of sequential parity checkers.
13. The notations used for state machines.
14. Moore and Mealy machines, examples.
15. Review of the basic method to calculate the excitation functions for Mealy machines.
16. Timing analysis of Mealy machine.
17. Schematics of Finite State Machines and their analysis.
18. FSMs as sequence transformers, acceptors and generators, time analysis.
19. Complete sets of gates, examples: NAND, NOR, AND/OR/NOT, AND/EXOR/1.
20. Incompletely specified functions.
21. Simple methods of EXOR-based synthesis by Kmap methods.
22. Factorization of multi-output functions.
23. Inhibition methods that use NAND and NOR gates.

READING ASSIGNMENT

1. Read chapter 4 from Wakerly.
2. Do as many practice problems as necessary to become fluent in SOLVING problems. You only learn by SOLVING problems and VERIFYING your solutions.

MANDATORY SLIDES

1. PDF. L011.prn.pdf. MSI (Middle Scale of Integration) Building Blocks: Mux, Demultiplexers, ROMs.
2. PDF. L012.prn.pdf. Memory Devices for Sequential Circuits: Latches and Flip-Flops.
3. PDF. L013.prn.pdf. Memory Devices for Sequential Synchronous Circuits: Excitation Functions of Flip-Flops.

LECTURES 4 and 5:

REVIEW AND COMBINATIONAL LOGIC IN SYNCHRONOUS CIRCUITS.

• CONCEPTS TO BE COVERED.
  1. Short review of minterms, prime implicants, essential prime implicants, K-map minimizaton of boolean fuctnions of single-output and multi-output functions.
  2. One example of a multi-output functions minimized separately and then using shared terms. Comparison of cost of these two ways of minimization.
  3. The concept of PLA, the function from the previous example represented as a PLA.
  4. Espresso format, the outline of Espresso procedure of minimization.
  5. MUXes (as selectors), deMUXes (as decoders). Cascading decoders.
  6. Incomplete decoders. Everything in gate-level schematics.
  7. The number of boolean functions for n-variables. Complete system of operations. Proof for {1,AND,EXOR}
  8. Implementation using NAND and NOR. The rule of the thumb,
  9. POS->NOR, SOP->NAND.
  10. Two major examples from the book of mapping multi-output functions using NAND and NOR.

  READING ASSIGNMENT

  1. Review chapter 7 from Wakerly. Do not read about Verilog, VHDL or Abel.
  2. Review material from class and slides.

HOMEWORK TWO

1. Word. Homework 2 about Generalized Registers.

REVIEW.

CONCEPTS TO BE COVERED.

1. SAT and Tautology.
2. Circuits with AND and EXOR gates.
3. Designing with one large MUX.
4. BDDs. Design BDD from equations. Convert BDD to a circuit from one-address multiplexers.
   Lecture about BDD and multiplexers in synthesis. The knowledge about BDD and MUX is mandatory. The knowledge about pass transitor and CMOS logic is additional and will be not required on tests.
   
5. Designing with MUX and gates. Expanding functions with respect to subsets of variables.
6. Various patters of control variables on a Kmap.
7. Use of MUXes for hierarchical decomposition.
8. D flip-flops.
9. Combining various logic synthesis methods.
10. Iterative circuits: carry in one or in two directions.
11. The need for verification. Verification methods: graphical versus symbolic.
12. Shift registers and Johnson Counters.
13. Generalized registers based on D ffs and MUX.
14. Generalized registers with non-bit-wise operations.

LECTURES 6 and 7:

GENERALIZED REGISTERS AND SYNCHRONOUS COUNTERS.

MANDATORY SLIDES

1. PDF. L017.prn.pdf. Arithmetic Circuits: Full Adder, Adder/Subtractor, Ripple Carry Chain, Carry Look-Ahead, Carry Select.
2. PDF. L018.prn.pdf. Arithmetic Circuits: Serial Adder, ALU, Parity, Comparators, Multipliers.
3. PDF. L019.prn.pdf. Medium Scale Integration (MSI) integrated circuits (ICs): Sequential Devices, registers and various shift registers.

READING ASSIGNMENT:

REVIEW

HOMEWORK THREE

1. Word. Homework 3 about FSMs, counters, analysis and simple data path design. This is material for quizz 3 and midterm 1.

LECTURES 8 and 9:

ITERATIVE CIRCUITS VERSUS SEQUENTIAL CIRCUITS.

READING ASSIGNMENT.

I give materials for Midterm 1 below.

CONCEPTS TO BE COVERED.

1. Solve three arbitrary problems that have solutions and check them.
2. Design of counters with large sequences.
3. Systematic Procedures for designing state machines with D, T and JK flip-flops.
4. Method with bold symbols. Selection of the best flip-flop.
5. Designing a flip-flop from another flip-flop.
6. Review on generalized registers: combining generalized registers with counters and adders.
7. Systematic versus ad hoc methods for designing state machines.
8. K-Map type of problems, versus Generalized Register type of problems.
9. Design of sequence acceptors and sequence generators.
10. Iterative Circuits. Addition, comparison,
11. Iterative circuits. Use of State Tables for Iterative Logic - repetition.
12. Register transfer using Shift registers.
13. Arithmetic and logic operations using Shift registers.
14. Relations between state machines and iterative circuits.

MANDATORY SLIDES

1. PDF. L020.prn.pdf. Design Example: Modulo 10 Counter with 7-Segment Display.
2. PDF. L014.prn.pdf. Synchronous Sequential Machines.
3. PDF. L015.prn.pdf. Design Examples of Simple Sequential Synchronous Machines.
4. PDF. L016.prn.pdf. Programmable Logic Devices: PAL, PLA, FPGA.

AUXILIARY SLIDES

1. Latches and timing - Wakerly Chapter_08.ppt
2. Counters and shifters - Wakerly Chapter_08.ppt
3. LFSR - Wakerly Chapter_08.ppt
4. clocks and metastability - Wakerly Chapter_08.ppt

REVIEW MATERIALS FOR MIDTERM ONE

1. Karnaugh Maps and their use - problems to solve.
2. 002. Examples to Midterm 1 - Kmaps and their uses - easy.ppt
3. 003. Examples to Midterm 1 - Advanced Minimization,Kmaps - EXOR - factorization.ppt
4. 004. Examples to Midterm 1 - Problems SOP.ppt
5. 005. Examples to Midterm 1. Problems. Multi-output SOP.ppt
6. 006. Examples to Midterm 1 - multi-level logic.ppt
7. 007. Examples to Midterm 1 - Multi-level synthesis from various gates.ppt
8. 008. Examples to Midterm 1 - Iterative circuits-mux-adders.ppt
9. 009. Examples to Midterm 1 = Problems- adders and seven segment displays.ppt
10. 010. Examples to Midterm 1 - Mux demultiplexers and ROMs.ppt
11. 011. Examples to Midterm 1 - numbers - decoders - functions.ppt
12. 012. Examples to Midterm 1 - problems from Hintz.ppt
13. 013. Design Example. Counter with 7 segment display.ppt
14. 014. Examples to Midterm 1 - simple FSM design.ppt
15. 015. Examples to Midterm 1 - More good FSM examples.ppt

More review MATERIALS FOR MIDTERM ONE

1. Midterm 1 for class 271 in last year.
2. ECE 271 Modulo-49 counter.pptx
3. Design of a vending machine using a PLA based FSM.
4. Examples of synthesis and analysis of Finite State Machines.
5. Big selection of mostly easy Problems for Midterm 1.
6. Design of comparator and multiplier.
7. Examples of various state machines and problems that can be realized as state machines for exams.
8. Solutions to homework 2 from Wakerly from last year.
9. Five problems from Midterm exam in other University.
10. Problems from Midterm 1 in earlier year.

ADVANCED ADDITIONAL MATERIALS FOR MIDTERM ONE

1. Use of state machine concepts in programming of computer games.
2. FSMs and Scripts for computer games.
3. Finite State Machines examples. One Hot Encoding.
4. State Machines in Graphics.
5. Mealy and Moore state machines and their programming in VHDL.
6. homework01_extracredit02_publishable.pdf
7. homework01_publishable.pdf
8. homework02_publishable.pdf
9. mealy_vs_moore.pdf

LECTURE 10.

MIDTERM 1. BASIC DESIGN OF ITERATIVE CIRCUITS AND SYNCHRONOUS FSMS.

LECTURES 18, 19 and 20:

REVIEW OF VERILOG WITH APPLICATIONS, VERILOG FOR SEQUENTIAL CIRCUITS.

READING ASSIGNMENT:

1. History.
2. Defining Module and Ports.
3. Types of design flows (behavioral and structural data flow).
4. Assign statement (design of combinational circuits).
5. Alawys Block.
6. Flip-Flop Design.
7. Introduction to writing test benches.
8. Iinitial block.

MANDATORY SLIDES: VERILOG.

SLIDES: Verilog Lecture in PDF


1. SLIDES POWERPOINT: Verilog Lecture in PPT Verilog Language. Structural Modeling. Behavioral Modeling. How Verilog is used. Two Main Components of Verilog. Two Main Data Types. Discrete-Event Simulation. Four-Valued Data. Four-Valued Logic. Structural Modeling. Nets and Registers. Modules and Instances. Instantiating a Module. Gate-Level Primitives. Delays on Primitive Instances. User-Defined Primitives. A Carry Primitive. A Sequential Primitive. Continuous Assignment. Behavioral Modeling. Initial and Always Blocks. Procedural Assignment. Imperative Statements. For Loops. While Loops. Modeling a FLIP-FLOP With Always. Blocking vs Non-Blocking. A Flawed Shift Register. Non-Blocking Assignments. Non-Blocking Can Behave oddly. Non-blocking Looks Like Latches. Building Behavioral Models. Modeling FSM Behaviorally. FSM with Combinational Logic. FSM from Combinational Logic. FSM from a Single Always Blocks. Simulating VERILOG. How are simulator used. Writing Testbenches. Simulation behavior. Two Types of events. Simulation behavior. Verilog and Logic Synthesis. Translating VERILOG into Gates. What can be translated. What isn't translated? Register Inference. Inferring Latches with Reset. Simulation-Synthesis Mismatches. Compared to VHDL.
   
   

   MANDATORY SLIDES ON COMBINATIONAL BLOCKS AND THEIR DESCRIPTION IN VERILOG.

   1. Verilog combinational blocks. Wakerly Chapter_06.ppt"
   2. XOR - Tree and Iterative circuits from Wakerly Chapter_06.ppt
   3. basic adders and multipliers from Wakerly.ppt
   4. Additional - Advanced Arithmetic Circuits.ppt
   5. Additional - Arithmetic Circuits. Comparators and ALU.ppt

   ADDITIONAL MATERIALS ON VERILOG.

   1. VerilogSim.htm Using Verilog in Intel Lab at PSU.
   2. Verilog_intro.pdf Verilog Slides.
   3. Verilog_intro_and_FSM.pdf
   4. adder.v Adder in Verilog.
   5. verilog_fsm_talk.pdf Describing FSMs in Verilog by Dr. Greenwood.
   6. verilogger_verilog_simulator.htm Verilog Simulator.
   7. add_sig.doc
   8. test_adder.v
2. AUXILIARY SLIDES ON VHDL. NOT FOR EXAMS. NOT FOR CLASS.
   1. PDF. L029.VHDL.pdf.prn.pdf VHDL

WEEK OF FINALS. DATE TO BE ANNOUNCED.

Final Exam

SPECIFICALLY TO REVIEW FOR FINAL:
1. All necessary final exam material is in the lecture slides above.
   1. Synchronized Flip-flops. T. D. JK.
   2. Iterative circuits and their relations to state machines.
   3. Counters. You have to be able to design an arbitrary counter.
   4. Sequential circuits such as sequence recognizers.

1. You can bring computer, slides, books, all materials that you want.
2. However, bringing the book is of little use if you do not know what is where.
3. I strongly suggest to have a creepsheet and a set of solved problems to use.
4. It is also good to have formatted Kmaps to use and color pencils to show groups.

You can reach me at
mperkows@ee.pdx.edu