BACK TO MAIN PAGE OF Professor Marek Perkowski.
Our standard class meetings are in room EB 103, Mondays, Wednesdays 1:003:20pm.
My email is mperkows@ee.pdx.edu.
Our additional meetings are in room FAB 150, Fridays 57pm.
Ms Sophie Choe, the class TA and grader has her office hours on Thursdays, 4:00 6:00 in room 100.
Her email is sophchoe@pdx.edu . PLEASE USE THIS OPORTUNITY TO LEARN MORE.
TEXTBOOK: John F. Wakerly. Digital Design. Principles and Practices. Fourth Edition.
Remember, that the main reading material is the Wakerly's Book. You can learn, however, all material from class slides only.
This book will be used in ECE 271 as well. So it is worthy to purchase.
The material given below is only auxiliary, to help you extend knowledge from the book.
How to learn for this class.
This class includes much material and is fast paced.
You have to read the mandatory slides before each lecture.
If I have no time to complete the slides, you are supposed to read this material on your own.
Do not read the book linearly. Read the material that you need to understand slides in full detail.
If you read both the book and my slides carefully
and you are able to solve the problems that you can find in this webpage,
then do not worry about your grade.
FOR YEAR 2017. MANDATORY LECTURES FOR THE ECE 171 CLASS TAUGHT BY DR. MAREK A. PERKOWSKI
The schedule of the meetings may change.
The class is graded on Midterm, homeworks and projects and final. There are no unexpected quizzes this year.
There is only one Midterm.
MEETING 1
 Lecture1 Number Systems.pptx
 TOPICS: Class introduction. Radix number representation. Binary, octal, hexadecimal. Fixed point numbers. Radix conversions.
 TOPICS: Explanation of my webpage, password and how to use the page.
 ASSIGNMENTS. Read Administration and Syllabus on this web site.
 ASSIGNMENTS. Read Wakerly. Sections 1.1  1.2 2.1  2.3.
 HOMEWORK. due xxx
MEETING 2
 Lecture2 Binary Arithmetics.pptx
 TOPICS: Representing negative numbers. Sign/magnitude. Ones complement. Binary addition, subtraction, overflow. Sign extension.
 ASSIGNMENTS. Read Wakerly, Sections 2.4  2.6.
 HOMEWORK. due xxx
MEETING 3
 Lecture3 Floating Point and Codes.pptx
 TOPICS: IEEE 754 Floating Point Standard. BCD, ASCII, Gray 754 Floating Point Standard.
 TOPICS: Seven segment display code.
 TOPICS: onehot and moutofn codes. Serial line codes.
 ASSIGNMENTS. Read Wakerly, Sections 2.102.12, 2.15.7, 2.16.
 HOMEWORK. due xxx
MEETING 4
 Lecture4 Boolean Algebra.pptx
 TOPICS: Boolean Algebra. Huntington's postulates. Truth Tables, schematic symbols.
 ASSIGNMENTS. Read Wakerly, Section 4.1.
 HOMEWORK. due xxx
MEETING 5
 Lecture5 Boolean Equations and KMaps.pptx
 TOPICS: Canonical Sum of Products form. Product of Sums form.
Compact minterm and maxterm forms. Logic Minimization in Karnaugh Maps. Product term sharing.
 ASSIGNMENTS. Read Wakerly, Section 4.3.
 HOMEWORK. due xxx
MEETING 6
 Lecture6 Symbols, Analysis, Design, NANDs.pptx
 TOPICS: Schematic symbols. Switching circuits. Schematic diagrams. Equivalent symbols.
NAND/NAND and NOR/NOR implementation.
 ASSIGNMENTS. Read Wakerly, Sections
3.13.3, 3.3.2 3.3.4, 4.2, 6.1.2.
 HOMEWORK. due xxx
MEETING 7
 Lecture7 Integrated Circuits.pptx
 TOPICS: Implementing logic. Integrated circuits. Printed Circuit Boards.
Logic families. Datasheets.
 ASSIGNMENTS. Read Wakerly, Sections 1.61.9, 4.3.1  4.3.2. 3.4.
 HOMEWORK. due xxx
MEETING 8
 Lecture8 Verilog.pptx
 TOPICS: Hardware Description Languages. Verilog. Dataflow Descriptions.
 ASSIGNMENTS. Read Wakerly, Sections 5.1, 5.4.15.4.6, 5.4.8, 5.4.11  5.4.13.
 PROJECT. due xxx
 EXAMPLE PROJECT SOLUTION.
MEETING 9. MIDTERM
 Covers all material to present except VERILOG. Open Book. Open Notes. No computers, calculators, phones or other devices.
 Bring ASCII chart/table.
MEETING 10
 More Verilog.
 TOPICS: Structural descriptions. Testbench techniques. Timing Diagrams. Midterm Exam solutions.
 TOPICS: Midterm Exam solutions.
 ASSIGNMENTS. Read Wakerly, Sections 5.4.7, 5.4.9.
MEETING 11
 Lecture 9 Hazards Decoders Multiplexers.pptx
 TOPICS: Glitches and Hazards. Static and Dynamic Hazards. Avoiding dynamic hazards, eliminating logic hazards. Decoders and Multiplexers.
Universal function implementers.
 ASSIGNMENTS. Read Wakerly, Sections 4.4, 6.4.1, 6.7.1.
 HOMEWORK. due xxx
MEETING 12
 Lecture 10 ROM PLA PAL PLD.pptx
 TOPICS: PLA, PROM, PAL, GAL. CPLDs.
 ASSIGNMENTS. Read Wakerly, Sections 6.3.1  6.3.4.
 HOMEWORK. due xxx
MEETING 13.
 Lecture 11 Blocks Decoders Demux.pptx
 TOPICS: Open Collector, Open Drain, Tristate Outputs. Tristate buffers. Bus outputs. Multiplexers.
 TOPICS: Decoders. XOR and XNOR. Parity.
 ASSIGNMENTS. Read Wakerly, Sections 3.7.33.7.7, 6.6.1, 6.7.3, 6.8.1, 6.8.2, 6,8,4.
 PROJECT 2. Testbench for Project 2.
MEETING 14.
 Lecture12 Adders Multipliers.pptx
 TOPICS: Modular design. Half adders. Full adders. Subtractors.
 ASSIGNMENTS. Read Wakerly, Sections 6.10.1.
 HOMEWORK. due xxx
MEETING 15.
 Ripple Carry Adders.
 Carry Lookahead Adders.
 ASSIGNMENTS. Read Wakerly, Sections 6.10.2, 6.10.4.
 HOMEWORK. due xxx
MEETING 16.
 TOPICS: Multipliers. ALU design.
 ASSIGNMENTS. Read Wakerly, Sections 6.10.6.
 HOMEWORK. due xxx
MEETING 17.
 Lecture 13 State Machines.pptx
 TOPICS: Latches. Flipflops. Clocks. State Machines. State Transition Diagrams.
 TOPICS: PS/NS stables. Counters.
 ASSIGNMENTS. Read Wakerly, Sections 7.2.1  7.2.6, 7.2.10  7.2.11, 7.3.
 HOMEWORK. due xxx
MEETING 18.
 TOPICS: Review of State Machines.
 ASSIGNMENTS. Read Wakerly, Section 7.5.
MEETING 19.
 TOPICS: Review before Final Exam. All material.
MEETING 20. FINAL EXAM.
 Comprehensive. Covers all material except Verilog.
 Open Book. Open notes.
 No computers or phones.
 Bring 74HCT08 datasheet.
 Bring Scantron Form 882E (available in PSU bookstore).
WARNING.
MATERIAL BELOW THIS LINE IS NOT MANDATORY.
WARNING.
MATERIAL BELOW THIS LINE IS NOT MANDATORY.
IT IS ADDED JUST TO HELP YOU BEING ABLE TO BETTER SOLVE MORE ADVANCED PROBLEMS.

##### REVIEW MATERIAL FOR MIDTERM. #####
 Most Important Material for Midterm.
 Use of Kmaps and logic design.
 Boolean Laws and how to use them. Laws of EXOR logic and Boolean Algebra. De Morgan Rules.
 Synthesis of multipleoutput circuits. Common functions.
 Factorization and synthesis of multilevel circuts. Cost of gates  number of inputs to gates.
USEFUL TOOLS FOR PROBLEM SOLVING:
 blank_kmaps.pdf
This is a collection of Kmaps. Print it and copy. Use in homeworks, projects and exams.
 cheat_sheet.pdf
This is a cheat sheet. Use it in quizzes,homeworks, projects and exams.
Material on Combinational Logic and circuits to be covered in Midterm.
 Review of Karnaugh Maps: variables, literals, products, product implicants, Prime implicants, essential prime implicants.
 How to draw a Kmap.
 Finding good groups in a Kmap.
 Covering problem of minterms in Kmap.
 Various uses of Kmaps to design with Muxes.
 Analysis methods (based on Kmaps, netlists, expressions).
 The importance of good selection of the analysis method.
 The relations between analysis and synthesis.
 NAND and NOR gates. Their use.
 Incompletely specified functions.
 Complete sets of gates, examples: NAND, NOR, AND/OR/NOT, AND/EXOR/1.
 Simple methods of EXORbased synthesis by Kmap methods.
 Factorization of multioutput functions.
 Inhibition methods that use NAND and NOR gates.
 There will be additional points given for solving the problems.
CHALLENGE PROBLEM 1. VERY DIFFICULT. 20 points.
Given are two inverters and any number of twoinput gates OR and AND. Other gates are not allowed.
Realize the function A = NOT(a), B = NOT(b), C = NOT(c).
PROBLEM 2. QUITE EASY. 5 points.
Given is arbitrary graph with 4 nodes and 5 edges. The encoding of colors is : red=00, blue=01, yellow=11, green=10.
Design a combinational circuits, called the oracle, that will give 1 on output for every good coloring. Show all gates. Draw schematics for your given graph.
How to exercise this oracle? How to give all binary inputs to it? Write software or pseudocode. Show all solutions.
Challenge problems will be given for those of you who
enjoy creativity and problem solving and to find potential candidates for individual undergraduate honor work  research on new topics and study of new research areas.
 ADDITIONAL MATERIAL, NOT REQUIRED: Lecture about BDD and multiplexers in synthesis.
The knowledge about BDD is not mandatory.
The knowledge about pass transitor and CMOS logic is additional and will be not required on tests.
 Designing with MUX and gates. Expanding functions with respect to subsets of variables.
 Various patters of control variables on a Kmap.
 Use of MUXes for hierarchical decomposition.
 Combining various logic synthesis methods.
Material on FSMs and Sequential circuits to be covered in Final.
 Latches.
 FlipFlops.
 Synchronous Devices.
 Designing binary counters.
 Designing sequential parity checkers.
 Please look to data sheets at the bottom of this page for practical examples of logic and
sequential blocks, components, counters, etc.
 Read about sequential parity checkers.
 The notations used for state machines.
 Moore and Mealy machines, examples.
 Review of the basic method to calculate the excitation functions for Mealy machines.
 Timing analysis of Mealy machine.
 Review of Shifters.
 Analysis of autonomous FSM.
 Analysis of nonautonomous FSM: from schematic to state machine graph.
 Review of sequential parity checkers.
 Schematics of Finite State Machines and their analysis.
 FSMs as sequence transformers, acceptors and generators, time analysis.
 Solve three arbitrary problems that have solutions and check them.
 Design of counters with large sequences.
 Systematic Procedures for designing state machines with D, T and JK flipflops.
 Method with bold symbols. Selection of the best flipflop.
 Designing a flipflop from another flipflop.
 Review on generalized registers: combining generalized registers with counters and adders.
 Systematic versus ad hoc methods for designing state machines.
 Design of sequence acceptors and sequence generators.
 Register transfer using Shift registers.
 Arithmetic and logic operations using Shift registers.
 Relations between state machines and iterative circuits.
 The need for verification. Verification methods: graphical versus symbolic.
 Shift registers and Johnson Counters.
PROBLEMS FROM WAKERLY'S BOOK WITH SOLUTIONS.
Some of you ask for solutions to Wakerly problems.
I do not think that all are available. Here are all solutions to Wakerly that I have.
For more problems with solutions look to my lectures from this webpage below.
You should read all "Mandatory" lecture slides, but additional and auxiliary slides include many good problems to solve.
 Problems to chapter 4. Combinational Circuits.
 Problems to chapter 5. Combinational Circuits.
 Problems to chapter 7. Sequential Circuits.
 Problems to chapter 8. Sequential Circuits.
##### EXAM PROBLEMS ON COMBINATIONAL CIRCUITS. #####
This section includes typical problems on combinational circuits.
The slides below were added for your request.

Karnaugh Maps and their use  problems to solve.

002. Examples to Midterm 1  Kmaps and their uses  easy.ppt

003. Examples to Midterm 1  Advanced Minimization,Kmaps  EXOR  factorization.ppt

004. Examples to Midterm 1  Problems SOP.ppt

005. Examples to Midterm 1. Problems. Multioutput SOP.ppt

006. Examples to Midterm 1  multilevel logic.ppt

007. Examples to Midterm 1  Multilevel synthesis from various gates.ppt

008. Examples to Midterm 1  Iterative circuitsmuxadders.ppt

009. Examples to Midterm 1 = Problems adders and seven segment displays.ppt

010. Examples to Midterm 1  Mux demultiplexers and ROMs.ppt

012. Examples to Midterm 1  problems from Hintz.ppt
 Midterm 1 in last year.
 Big selection of mostly easy Problems for Midterm 1.
 Design of comparator and multiplier.
##### EXAM PROBLEMS ON STATE MACHINES. #####
 Modulo49 counter.pptx
 Design of a vending machine using a PLA based FSM.

Examples of synthesis and analysis of Finite State Machines.
 Examples of various state machines and problems that can be realized as state machines for exams.
 Solutions to homework 2 from Wakerly from last year.
 Five problems from Midterm 2 exam in other University.
 Problems from Midterm 2 in earlier year.
 Use of state machine concepts in programming of computer games.
 FSMs and Scripts for computer games.

Finite State Machines examples. One Hot Encoding.
 State Machines in Graphics.
 Mealy and Moore state machines and their programming
in VHDL.
 homework01_extracredit02_publishable.pdf
 homework01_publishable.pdf
 homework02_publishable.pdf
 mealy_vs_moore.pdf

013. Design Example. Counter with 7 segment display.ppt

014. Examples to Midterm 2  simple FSM design.ppt

015. Examples to Midterm 2  More good FSM examples.ppt
 Word. Homework 2 about Generalized Registers.
ADDITIONAL LECTURES AND PROBLEMS
##### ADDITIONAL MATERIAL TO LECTURES 1, 2 and 3. ##### INTRODUCTION TO CLASS, NUMBER SYSTEMS, CODES and BINARY ARITHMETICS.#####
 Introduction to class.
 Review and Short Overview.ppt
 Chapter_02.Wakerly.Number Systems.ppt
 001. Intro to number Systems.ppt
 Chapter_02 Number systems.ppt
 002. Wakerly. Positional Number Systems.ppt
 003. Wakerly Section 2.4 and further.ppt
##### ADDITIONAL MATERIAL TO LECTURES 4 and 5. ##### BOOLEAN ALGEBRA ##### BOOLEAN EQUATIONS AND KMAPS. #####
This lecture reviews basic material from ECE 171 that is necessary for practical homework
problems and projects.
More advanced synthesis methods will be next added and comments about their use in idustrial CAD systems.
 CONCEPTS TO BE COVERED.
 Truth Tables versus expressions versus Karnaugh Maps.
 Short intro to minterms, prime implicants, Kmap minimizaton of boolean fuctnions of singleoutput
and multioutput functions.
 The concept of verification by reduction to canonical forms.
 Homework 1 was assigned in class. It was related to SOP circuit realized with AND and OR gates
or NAND gates and POS circuits realized with AND and OR gates or NOR gates. It is due next Monday.
 Basic logic gates and circuits. Types of circuits. Problems.
 2010004.Basic gates.Wakerly.chpt2.ppt
 2010005. Wakerly  Chapter_03  logic gates.ppt
 Project Advise of old professor.ppt
 PDF. n4.prn.pdf. Boolean Algebra and Logic Operations. Fundamentals.
 PDF. L007.prn.pdf. Realization of Digital Circuits.
Logic Circuits, Truth Tables, KMaps, and ROMs.
 PDF. L008.prn.pdf. Minimization of Combinational Logic
Using KMaps. Fundamentals.
 PDF. L010.prn.pdf. MultipleOutput SOP (Sum of Products)
minimization. This lecture teaches you how to use Kmaps to solve multioutput functions.
 PDF. L009.prn.pdf. Additional Reading Material
about Combinational Circuit and Combinational Optimization and Decision
Problems. Set Covering, Petrick Function, Maximum Clique and Graph Coloring.
Unate and Binate Covering. These are advanced methods to solve covering tables. We use them also in test minimization.
FOR FUN AND ENTERTAINMENT: WALKING ROBOTS
 iSOBOT robot movie from PSU
 another iSOBOT robot movie from PSU
 KHR01 robot movie from PSU
 Niels Bohr robot movie from PSU
 robot movie , jumpiong robot from Japan
 robot movie
 robot movie
 robot movie
 robot movie
 robot movie
 robot movie
 robot movie
 robot movie
 robot movie
Additional advanced slides for students who want to do individual research
 Seminar by Perkowski about regular structures.
##### ADDITIONAL MATERIAL TO LECTURE 6. ##### SYMBOLS, ANALYSIS, DESIGN, NANDS, NORs. #####
 2010003.Basic gates.Wakerly.chpt2 NAND.ppt
##### ADDITIONAL MATERIAL TO LECTURE 7. ##### INTEGRATED CIRCUITS. #####
 Digital IC1.ppt
 Digital IC2.ppt
 Digital IC3.ppt
##### ADDITIONAL MATERIAL TO LECTURE 8. ##### VERILOG WITH APPLICATIONS, VERILOG FOR SEQUENTIAL CIRCUITS. #####
This lecture is about Verilog and its uses to describe combinational circuits and Finite State Machines.
READING ASSIGNMENT:
VERILOG.
 History.
 Defining Module and Ports.
 Types of design flows (behavioral and structural data flow).
 Assign statement (design of combinational circuits).
 Alawys Block.
 FlipFlop Design.
 Introduction to writing test benches.
 Iinitial block.
SLIDES: VERILOG.
Verilog Lecture in PDF
 SLIDES POWERPOINT:
Verilog Lecture in PPT
Verilog Language. Structural Modeling.
Behavioral Modeling. How Verilog is used. Two Main Components of Verilog.
Two Main Data Types. DiscreteEvent Simulation. FourValued Data.
FourValued Logic. Structural Modeling. Nets and Registers.
Modules and Instances. Instantiating a Module. GateLevel Primitives.
Delays on Primitive Instances. UserDefined Primitives.
A Carry Primitive. A Sequential Primitive. Continuous Assignment.
Behavioral Modeling. Initial and Always Blocks. Procedural Assignment.
Imperative Statements. For Loops. While Loops. Modeling a FLIPFLOP With Always.
Blocking vs NonBlocking. A Flawed Shift Register. NonBlocking Assignments.
NonBlocking Can Behave oddly. Nonblocking Looks Like Latches.
Building Behavioral Models. Modeling FSM Behaviorally. FSM with Combinational Logic.
FSM from Combinational Logic. FSM from a Single Always Blocks.
Simulating VERILOG. How are simulator used. Writing Testbenches.
Simulation behavior. Two Types of events. Simulation behavior. Verilog and Logic Synthesis.
Translating VERILOG into Gates. What can be translated. What isn't translated? Register Inference.
Inferring Latches with Reset. SimulationSynthesis Mismatches.
Compared to VHDL.
SLIDES ON COMBINATIONAL BLOCKS AND THEIR DESCRIPTION IN VERILOG.

Verilog combinational blocks. Wakerly Chapter_06.ppt"

XOR  Tree and Iterative circuits from Wakerly Chapter_06.ppt
ADDITIONAL MATERIALS ON VERILOG.
 FPGA_Verilog.pdf
 FSM Verilog.pdf
 typical problems in verilog=counters.pptx
 VerilogSim.htm Using Verilog in Intel Lab at PSU.
 Verilog_intro.pdf Verilog Slides.
 Verilog_intro_and_FSM.pdf
 adder.v Adder in Verilog.
 verilog_fsm_talk.pdf
Describing FSMs in Verilog by Dr. Greenwood.
 verilogger_verilog_simulator.htm
Verilog Simulator.
 add_sig.doc
 test_adder.v
 Asynchronous FSM . Verilog  Wakerly Chapter_07.ppt
 Good examples Verilog pipelined systolic multiplication.ppt
 AUXILIARY SLIDES ON VHDL. NOT FOR EXAMS. NOT FOR CLASS.
 PDF. L029.VHDL.pdf.prn.pdf VHDL
##### ADDITIONAL MATERIAL TO LECTURE 9. ##### HAZARDS, DECODERS, MULTIPLEXERS.

011. Examples to Midterm 1  numbers  decoders  functions.ppt
##### ADDITIONAL MATERIAL TO LECTURE 10. ##### ROM, PLA, PLD, PAL.
 PDF. L011.prn.pdf. MSI (Middle Scale of Integration) Building Blocks: Mux, Demultiplexers, ROMs.
##### ADDITIONAL MATERIAL TO LECTURE 11. ##### BLOCKS, DECODERS, DEMUX.

Verilog combinational blocks. Wakerly Chapter_06.ppt

XOR  Tree and Iterative circuits from Wakerly Chapter_06.ppt

Basic adders and multipliers from Wakerly.ppt

Asynchronous FSM . Verilog  Wakerly Chapter_07.ppt">
##### ADDITIONAL MATERIAL TO LECTURE 12. ##### ADDERS AND MULTIPLIERS. ALU.
 PDF. L017.prn.pdf. Arithmetic Circuits:
Full Adder, Adder/Subtractor, Ripple Carry Chain, Carry LookAhead, Carry Select.

basic adders and multipliers from Wakerly.ppt

Additional  Advanced Arithmetic Circuits.ppt

Additional  Arithmetic Circuits. Comparators and ALU.ppt
##### ADDITIONAL MATERIAL TO LECTURE 13. ##### FINITE STATE MACHINES.
This lecture reviews material from ECE 171 that you should be familiar with.
More advanced synthesis methods are alse added and comments about their use in idustrial CAD systems.
We discuss also simple state machines.
This lecture discusses advanced methods of combinational logic synthesis and their use in state machines.
You should be familiar with analysis of state machines.
SLIDES
 PDF. L012.prn.pdf. Memory Devices for
Sequential Circuits: Latches and FlipFlops.
 PDF. L013.prn.pdf. Memory Devices for Sequential
Synchronous Circuits: Excitation Functions of FlipFlops.
 Word. Homework 3 about FSMs, counters, analysis and simple data path design.
 PDF. L020.prn.pdf. Design Example: Modulo 10
Counter with 7Segment Display.
 PDF. L014.prn.pdf. Synchronous Sequential Machines.
 PDF. L015.prn.pdf. Design Examples of Simple Sequential Synchronous Machines.
 PDF. L016.prn.pdf. Programmable Logic Devices: PAL, PLA, FPGAs with flipflops.
 fpga.pdf
 2010007. easy state machine project.ppt
 2010008. robot arm control design.pdf
 2010009. Project Fuzzy Logics.pdf
 PDF. L018.prn.pdf. Arithmetic Circuits:
Serial Adder, ALU, Parity, Comparators, Multipliers.
 PDF. L019.prn.pdf. Medium Scale Integration (MSI)
integrated circuits (ICs): Sequential Devices, registers and various shift registers.
 ECE171 Student design project.ppt
 171 Student design project = Fibonacci Counter.pptx
WEEK OF FINALS.
Final Exam
This final exam will take exactly two hours.
This will be a comprehensive exam that will include the entire class material,
except Verilog.
In particular, the material from ALL LECTURES ,
the quizz, all homeworks, and the two midterms.
SPECIFICALLY TO REVIEW FOR FINAL:
 All necessary final exam material is in the lecture slides above.
 Synchronized Flipflops. T. D. JK.
 Counters. You have to be able to design an arbitrary counter.
 Sequential circuits such as sequence recognizers.
OPEN BOOK.
 You can bring computer, slides, books, all materials that you want.
 However, bringing the book is of little use if you do not know what is where.
 I strongly suggest to have a creepsheet and a set of solved problems to use.
 It is also good to have formatted Kmaps to use and color pencils to show groups.
GOOD LUCK. !!
Have a good vacation.
Check your grades on the door of my room or in ECE office, room 16005.
BACK TO MAIN PAGE OF Professor Marek Perkowski.
You can reach me at
mperkows@ee.pdx.edu