BACK TO MAIN PAGE OF Professor Marek Perkowski.

Our standard class meetings are in room EB 103, Mondays, Wednesdays 1:00-3:20pm.
My email is mperkows@ee.pdx.edu.

Our additional meetings are in room FAB 150, Fridays 5-7pm.

Ms Sophie Choe, the class TA and grader has her office hours on Thursdays, 4:00- 6:00 in room 100. Her email is sophchoe@pdx.edu . PLEASE USE THIS OPORTUNITY TO LEARN MORE.

TEXTBOOK: John F. Wakerly. Digital Design. Principles and Practices. Fourth Edition.
Remember, that the main reading material is the Wakerly's Book. You can learn, however, all material from class slides only. This book will be used in ECE 271 as well. So it is worthy to purchase.

The material given below is only auxiliary, to help you extend knowledge from the book.

How to learn for this class. This class includes much material and is fast paced. You have to read the mandatory slides before each lecture. If I have no time to complete the slides, you are supposed to read this material on your own. Do not read the book linearly. Read the material that you need to understand slides in full detail. If you read both the book and my slides carefully and you are able to solve the problems that you can find in this webpage, then do not worry about your grade.

# FOR YEAR 2017. MANDATORY LECTURES FOR THE ECE 171 CLASS TAUGHT BY DR. MAREK A. PERKOWSKI

The schedule of the meetings may change.
The class is graded on Midterm, homeworks and projects and final. There are no unexpected quizzes this year.
There is only one Midterm.

## MEETING 1

1. Lecture1 Number Systems.pptx
3. TOPICS: Explanation of my webpage, password and how to use the page.
5. ASSIGNMENTS. Read Wakerly. Sections 1.1 - 1.2 2.1 - 2.3.
6. HOMEWORK. due xxx

## MEETING 2

1. Lecture2 Binary Arithmetics.pptx
2. TOPICS: Representing negative numbers. Sign/magnitude. Ones complement. Binary addition, subtraction, overflow. Sign extension.
3. ASSIGNMENTS. Read Wakerly, Sections 2.4 - 2.6.
4. HOMEWORK. due xxx

## MEETING 3

1. Lecture3 Floating Point and Codes.pptx
2. TOPICS: IEEE 754 Floating Point Standard. BCD, ASCII, Gray 754 Floating Point Standard.
3. TOPICS: Seven segment display code.
4. TOPICS: one-hot and m-out-of-n codes. Serial line codes.
5. ASSIGNMENTS. Read Wakerly, Sections 2.10-2.12, 2.15.7, 2.16.
6. HOMEWORK. due xxx

## MEETING 4

1. Lecture4 Boolean Algebra.pptx
2. TOPICS: Boolean Algebra. Huntington's postulates. Truth Tables, schematic symbols.
3. ASSIGNMENTS. Read Wakerly, Section 4.1.
4. HOMEWORK. due xxx

## MEETING 5

1. Lecture5 Boolean Equations and KMaps.pptx
2. TOPICS: Canonical Sum of Products form. Product of Sums form. Compact minterm and maxterm forms. Logic Minimization in Karnaugh Maps. Product term sharing.
3. ASSIGNMENTS. Read Wakerly, Section 4.3.
4. HOMEWORK. due xxx

## MEETING 6

1. Lecture6 Symbols, Analysis, Design, NANDs.pptx
2. TOPICS: Schematic symbols. Switching circuits. Schematic diagrams. Equivalent symbols. NAND/NAND and NOR/NOR implementation.
3. ASSIGNMENTS. Read Wakerly, Sections 3.1-3.3, 3.3.2- 3.3.4, 4.2, 6.1.2.
4. HOMEWORK. due xxx

## MEETING 7

1. Lecture7 Integrated Circuits.pptx
2. TOPICS: Implementing logic. Integrated circuits. Printed Circuit Boards. Logic families. Datasheets.
3. ASSIGNMENTS. Read Wakerly, Sections 1.6-1.9, 4.3.1 - 4.3.2. 3.4.
4. HOMEWORK. due xxx

## MEETING 8

1. Lecture8 Verilog.pptx
2. TOPICS: Hardware Description Languages. Verilog. Dataflow Descriptions.
3. ASSIGNMENTS. Read Wakerly, Sections 5.1, 5.4.1-5.4.6, 5.4.8, 5.4.11 - 5.4.13.
4. PROJECT. due xxx
5. EXAMPLE PROJECT SOLUTION.

## MEETING 9. MIDTERM

1. Covers all material to present except VERILOG. Open Book. Open Notes. No computers, calculators, phones or other devices.
2. Bring ASCII chart/table.

## MEETING 10

1. More Verilog.
2. TOPICS: Structural descriptions. Testbench techniques. Timing Diagrams. Midterm Exam solutions.
3. TOPICS: Midterm Exam solutions.
4. ASSIGNMENTS. Read Wakerly, Sections 5.4.7, 5.4.9.

## MEETING 11

1. Lecture 9 Hazards Decoders Multiplexers.pptx
2. TOPICS: Glitches and Hazards. Static and Dynamic Hazards. Avoiding dynamic hazards, eliminating logic hazards. Decoders and Multiplexers. Universal function implementers.
3. ASSIGNMENTS. Read Wakerly, Sections 4.4, 6.4.1, 6.7.1.
4. HOMEWORK. due xxx

## MEETING 12

1. Lecture 10 ROM PLA PAL PLD.pptx
2. TOPICS: PLA, PROM, PAL, GAL. CPLDs.
3. ASSIGNMENTS. Read Wakerly, Sections 6.3.1 - 6.3.4.
4. HOMEWORK. due xxx

## MEETING 13.

1. Lecture 11 Blocks Decoders Demux.pptx
2. TOPICS: Open Collector, Open Drain, Tri-state Outputs. Tri-state buffers. Bus outputs. Multiplexers.
3. TOPICS: Decoders. XOR and XNOR. Parity.
4. ASSIGNMENTS. Read Wakerly, Sections 3.7.3-3.7.7, 6.6.1, 6.7.3, 6.8.1, 6.8.2, 6,8,4.
5. PROJECT 2. Testbench for Project 2.

## MEETING 14.

3. ASSIGNMENTS. Read Wakerly, Sections 6.10.1.
4. HOMEWORK. due xxx

## MEETING 15.

3. ASSIGNMENTS. Read Wakerly, Sections 6.10.2, 6.10.4.
4. HOMEWORK. due xxx

## MEETING 16.

1. TOPICS: Multipliers. ALU design.
2. ASSIGNMENTS. Read Wakerly, Sections 6.10.6.
3. HOMEWORK. due xxx

## MEETING 17.

1. Lecture 13 State Machines.pptx
2. TOPICS: Latches. Flip-flops. Clocks. State Machines. State Transition Diagrams.
3. TOPICS: PS/NS stables. Counters.
4. ASSIGNMENTS. Read Wakerly, Sections 7.2.1 - 7.2.6, 7.2.10 - 7.2.11, 7.3.
5. HOMEWORK. due xxx

## MEETING 18.

1. TOPICS: Review of State Machines.
2. ASSIGNMENTS. Read Wakerly, Section 7.5.

## MEETING 19.

1. TOPICS: Review before Final Exam. All material.

## MEETING 20. FINAL EXAM.

1. Comprehensive. Covers all material except Verilog.
2. Open Book. Open notes.
3. No computers or phones.
4. Bring 74HCT08 datasheet.
5. Bring Scantron Form 882-E (available in PSU bookstore).

# WARNING. MATERIAL BELOW THIS LINE IS NOT MANDATORY. IT IS ADDED JUST TO HELP YOU BEING ABLE TO BETTER SOLVE MORE ADVANCED PROBLEMS.

--------------------------------------------------------------------------------------------------------------

# ##### REVIEW MATERIAL FOR MIDTERM. #####

1. Most Important Material for Midterm.
2. Use of Kmaps and logic design.
3. Boolean Laws and how to use them. Laws of EXOR logic and Boolean Algebra. De Morgan Rules.
4. Synthesis of multiple-output circuits. Common functions.
5. Factorization and synthesis of multi-level circuts. Cost of gates - number of inputs to gates.

USEFUL TOOLS FOR PROBLEM SOLVING:
1. blank_kmaps.pdf This is a collection of Kmaps. Print it and copy. Use in homeworks, projects and exams.
2. cheat_sheet.pdf This is a cheat sheet. Use it in quizzes,homeworks, projects and exams.

Material on Combinational Logic and circuits to be covered in Midterm.
1. Review of Karnaugh Maps: variables, literals, products, product implicants, Prime implicants, essential prime implicants.
2. How to draw a Kmap.
3. Finding good groups in a Kmap.
4. Covering problem of minterms in Kmap.
5. Various uses of Kmaps to design with Muxes.
6. Analysis methods (based on Kmaps, netlists, expressions).
7. The importance of good selection of the analysis method.
8. The relations between analysis and synthesis.
9. NAND and NOR gates. Their use.
10. Incompletely specified functions.
11. Complete sets of gates, examples: NAND, NOR, AND/OR/NOT, AND/EXOR/1.
12. Simple methods of EXOR-based synthesis by Kmap methods.
13. Factorization of multi-output functions.
14. Inhibition methods that use NAND and NOR gates.
15. There will be additional points given for solving the problems.
CHALLENGE PROBLEM 1. VERY DIFFICULT. 20 points. Given are two inverters and any number of two-input gates OR and AND. Other gates are not allowed. Realize the function A = NOT(a), B = NOT(b), C = NOT(c).
PROBLEM 2. QUITE EASY. 5 points. Given is arbitrary graph with 4 nodes and 5 edges. The encoding of colors is : red=00, blue=01, yellow=11, green=10. Design a combinational circuits, called the oracle, that will give 1 on output for every good coloring. Show all gates. Draw schematics for your given graph. How to exercise this oracle? How to give all binary inputs to it? Write software or pseudo-code. Show all solutions.
Challenge problems will be given for those of you who enjoy creativity and problem solving and to find potential candidates for individual undergraduate honor work - research on new topics and study of new research areas.
16. ADDITIONAL MATERIAL, NOT REQUIRED: Lecture about BDD and multiplexers in synthesis. The knowledge about BDD is not mandatory. The knowledge about pass transitor and CMOS logic is additional and will be not required on tests.
17. Designing with MUX and gates. Expanding functions with respect to subsets of variables.
18. Various patters of control variables on a Kmap.
19. Use of MUXes for hierarchical decomposition.
20. Combining various logic synthesis methods.
Material on FSMs and Sequential circuits to be covered in Final.
1. Latches.
2. Flip-Flops.
3. Synchronous Devices.
4. Designing binary counters.
5. Designing sequential parity checkers.
6. Please look to data sheets at the bottom of this page for practical examples of logic and sequential blocks, components, counters, etc.
8. The notations used for state machines.
9. Moore and Mealy machines, examples.
10. Review of the basic method to calculate the excitation functions for Mealy machines.
11. Timing analysis of Mealy machine.
12. Review of Shifters.
13. Analysis of autonomous FSM.
14. Analysis of non-autonomous FSM: from schematic to state machine graph.
15. Review of sequential parity checkers.
16. Schematics of Finite State Machines and their analysis.
17. FSMs as sequence transformers, acceptors and generators, time analysis.
18. Solve three arbitrary problems that have solutions and check them.
19. Design of counters with large sequences.
20. Systematic Procedures for designing state machines with D, T and JK flip-flops.
21. Method with bold symbols. Selection of the best flip-flop.
22. Designing a flip-flop from another flip-flop.
23. Review on generalized registers: combining generalized registers with counters and adders.
24. Systematic versus ad hoc methods for designing state machines.
25. Design of sequence acceptors and sequence generators.
26. Register transfer using Shift registers.
27. Arithmetic and logic operations using Shift registers.
28. Relations between state machines and iterative circuits.
29. The need for verification. Verification methods: graphical versus symbolic.
30. Shift registers and Johnson Counters.

## PROBLEMS FROM WAKERLY'S BOOK WITH SOLUTIONS.

Some of you ask for solutions to Wakerly problems. I do not think that all are available. Here are all solutions to Wakerly that I have. For more problems with solutions look to my lectures from this webpage below. You should read all "Mandatory" lecture slides, but additional and auxiliary slides include many good problems to solve.

## ##### EXAM PROBLEMS ON COMBINATIONAL CIRCUITS. #####

This section includes typical problems on combinational circuits. The slides below were added for your request.

## ##### ADDITIONAL MATERIAL TO LECTURES 4 and 5. ##### BOOLEAN ALGEBRA ##### BOOLEAN EQUATIONS AND KMAPS. #####

This lecture reviews basic material from ECE 171 that is necessary for practical homework problems and projects. More advanced synthesis methods will be next added and comments about their use in idustrial CAD systems.
1. CONCEPTS TO BE COVERED.
2. Truth Tables versus expressions versus Karnaugh Maps.
3. Short intro to minterms, prime implicants, K-map minimizaton of boolean fuctnions of single-output and multi-output functions.
4. The concept of verification by reduction to canonical forms.
5. Homework 1 was assigned in class. It was related to SOP circuit realized with AND and OR gates or NAND gates and POS circuits realized with AND and OR gates or NOR gates. It is due next Monday.
6. Basic logic gates and circuits. Types of circuits. Problems.
7. 2010-004.Basic gates.Wakerly.chpt2.ppt
8. 2010-005. Wakerly - Chapter_03 - logic gates.ppt
9. Project Advise of old professor.ppt
10. PDF. n4.prn.pdf. Boolean Algebra and Logic Operations. Fundamentals.
11. PDF. L007.prn.pdf. Realization of Digital Circuits. Logic Circuits, Truth Tables, K-Maps, and ROMs.
12. PDF. L008.prn.pdf. Minimization of Combinational Logic Using K-Maps. Fundamentals.
13. PDF. L010.prn.pdf. Multiple-Output SOP (Sum of Products) minimization. This lecture teaches you how to use Kmaps to solve multi-output functions.
14. PDF. L009.prn.pdf. Additional Reading Material about Combinational Circuit and Combinational Optimization and Decision Problems. Set Covering, Petrick Function, Maximum Clique and Graph Coloring. Unate and Binate Covering. These are advanced methods to solve covering tables. We use them also in test minimization.

FOR FUN AND ENTERTAINMENT: WALKING ROBOTS

## ##### ADDITIONAL MATERIAL TO LECTURE 8. ##### VERILOG WITH APPLICATIONS, VERILOG FOR SEQUENTIAL CIRCUITS. #####

This lecture is about Verilog and its uses to describe combinational circuits and Finite State Machines.

VERILOG.
1. History.
2. Defining Module and Ports.
3. Types of design flows (behavioral and structural data flow).
4. Assign statement (design of combinational circuits).
5. Alawys Block.
6. Flip-Flop Design.
7. Introduction to writing test benches.
8. Iinitial block.

### SLIDES: VERILOG.

Verilog Lecture in PDF

1. SLIDES POWERPOINT: Verilog Lecture in PPT Verilog Language. Structural Modeling. Behavioral Modeling. How Verilog is used. Two Main Components of Verilog. Two Main Data Types. Discrete-Event Simulation. Four-Valued Data. Four-Valued Logic. Structural Modeling. Nets and Registers. Modules and Instances. Instantiating a Module. Gate-Level Primitives. Delays on Primitive Instances. User-Defined Primitives. A Carry Primitive. A Sequential Primitive. Continuous Assignment. Behavioral Modeling. Initial and Always Blocks. Procedural Assignment. Imperative Statements. For Loops. While Loops. Modeling a FLIP-FLOP With Always. Blocking vs Non-Blocking. A Flawed Shift Register. Non-Blocking Assignments. Non-Blocking Can Behave oddly. Non-blocking Looks Like Latches. Building Behavioral Models. Modeling FSM Behaviorally. FSM with Combinational Logic. FSM from Combinational Logic. FSM from a Single Always Blocks. Simulating VERILOG. How are simulator used. Writing Testbenches. Simulation behavior. Two Types of events. Simulation behavior. Verilog and Logic Synthesis. Translating VERILOG into Gates. What can be translated. What isn't translated? Register Inference. Inferring Latches with Reset. Simulation-Synthesis Mismatches. Compared to VHDL.

### SLIDES ON COMBINATIONAL BLOCKS AND THEIR DESCRIPTION IN VERILOG.

1. FPGA_Verilog.pdf
2. FSM Verilog.pdf
3. typical problems in verilog=counters.pptx
5. Verilog_intro.pdf Verilog Slides.
6. Verilog_intro_and_FSM.pdf
8. verilog_fsm_talk.pdf Describing FSMs in Verilog by Dr. Greenwood.
9. verilogger_verilog_simulator.htm Verilog Simulator.
12. Asynchronous FSM . Verilog - Wakerly Chapter_07.ppt
13. Good examples Verilog pipelined systolic multiplication.ppt
14. AUXILIARY SLIDES ON VHDL. NOT FOR EXAMS. NOT FOR CLASS.
15. PDF. L029.VHDL.pdf.prn.pdf VHDL

## ##### ADDITIONAL MATERIAL TO LECTURE 11. ##### BLOCKS, DECODERS, DEMUX.

1. Verilog combinational blocks. Wakerly Chapter_06.ppt
2. XOR - Tree and Iterative circuits from Wakerly Chapter_06.ppt
3. Basic adders and multipliers from Wakerly.ppt
4. Asynchronous FSM . Verilog - Wakerly Chapter_07.ppt">

## ##### ADDITIONAL MATERIAL TO LECTURE 13. ##### FINITE STATE MACHINES.

This lecture reviews material from ECE 171 that you should be familiar with. More advanced synthesis methods are alse added and comments about their use in idustrial CAD systems. We discuss also simple state machines. This lecture discusses advanced methods of combinational logic synthesis and their use in state machines. You should be familiar with analysis of state machines.

# Final Exam

This final exam will take exactly two hours.

EXAM
This will be a comprehensive exam that will include the entire class material,
except Verilog.
In particular, the material from ALL LECTURES , the quizz, all homeworks, and the two midterms.

SPECIFICALLY TO REVIEW FOR FINAL:
1. All necessary final exam material is in the lecture slides above.
1. Synchronized Flip-flops. T. D. JK.
2. Counters. You have to be able to design an arbitrary counter.
3. Sequential circuits such as sequence recognizers.

OPEN BOOK.
1. You can bring computer, slides, books, all materials that you want.
2. However, bringing the book is of little use if you do not know what is where.
3. I strongly suggest to have a creepsheet and a set of solved problems to use.
4. It is also good to have formatted Kmaps to use and color pencils to show groups.

GOOD LUCK. !!

Have a good vacation.

Check your grades on the door of my room or in ECE office, room 160-05.

BACK TO MAIN PAGE OF Professor Marek Perkowski.
You can reach me at
mperkows@ee.pdx.edu