PROFESSOR MAREK PERKOWSKI: SORTERS: FOR HOMEWORK NUMBER ONE.

PROJECTS RELATED TO HOMEWORK 1: Investigating Design Tradeoffs.

The goal of this project is to investigate design trade-offs:
combinational/sequential.
iterative circuit/finite state machine with the same logic as the cell of iterative circuit.
parallel versus sequential versus counter arithmetics. Pulse arithmetics. Pseudo-analog circuits.
Simple SIMD versus pipelined machines.
    Traditionally, we designed a sorter or a simplified logic machine in this project.
  1. SORTER/ABSORBER FOR BOOLEAN MINIMIZATION.
    1. Sorter/Absorber by Pavel Kashubin and Edward Tuers, 1997.
    2. New sorter of Kashubin
  2. MODEL OF A RAM FOR SORTER.
    1. PROJECT: RAM Model. To be used in a sorter.
  3. SORTER BY RAM KOGANTI'S GROUP.
    1. Sorter by Ram Koganti. Report in Postscript.
    2. Schematic in Postscript.
  4. SORTER BY YVONNE YANG
    1. VHDL code
    2. Sorter by Yvonne Yang Yvonne Yang's sorter.
  5. SORTER BY WEI WANG'S GROUP.
    1. Wei Wang HOMEWORK 1: Sorter.
  6. PIPELINED SORTER
    1. PROJECT 1-2 Pipelined Sorter.
  7. COMBINATIONAL SORTER
    1. PROJECT 1-3 Combinational Sorter.
  8. COMBINATIONAL SORTER
    1. PROJECT 1-4 Sorter based on standard controller.