NICK ILIEV RAM.
 
A simple RAM model , based on a 1D array, which is
easy to write/read with separate processes. This is only
an example of a 32x4-bit memory, but can easily be extended
to 256x256x4-bits. A testbench is attached as well :

--- ram1.vhd
-- RAM model 32 4-bit words
-- LOW_CS is active-low Chip Select
use work.all;
entity RAM1 is
   generic ( RDEL, DISDEL : TIME);
   port ( DATA_IN : in BIT_VECTOR ( 3 downto 0);
          DATA_OUT : out BIT_VECTOR ( 3 downto 0);
          ADDRESS : in BIT_VECTOR (4 downto 0) ;
          RD,WR, LOW_CS : in BIT );
end RAM1;

architecture RAM_ALG  of RAM1 is
   function INTVAL ( VAL : BIT_VECTOR ) return INTEGER is
   variable VALV : BIT_VECTOR ( VAL'LENGTH -1 downto 0 );
   variable SUM : INTEGER := 0;
   begin
      VALV := VAL;
      for N in VALV'LOW to VALV'HIGH loop
        if VALV(N) = '1' then
          SUM := SUM + (2**N);
          end if;
      end loop;
      return SUM;
   end INTVAL;

   type MEMORY is array ( 0 to 31) of BIT_VECTOR ( 3 downto 0);
   signal MEM : MEMORY;
begin
        process ( RD, WR, LOW_CS, ADDRESS, DATA_IN)
        begin
           if LOW_CS = '0' then
             if RD = '1' then
               DATA_OUT <= MEM( INTVAL(ADDRESS) ) after RDEL;
             elsif WR = '1' then
               MEM ( INTVAL ( ADDRESS ) ) <= DATA_IN;
             end if; -- if RD
           else
             DATA_OUT <= "1111" after DISDEL;
            end if; -- if LOW_CS
           end process;
end RAM_ALG;


--------- tram1.vhd  testbench ------
-- Test bench for RAM1
use work.all;
entity TB_RAM1 is
end TB_RAM1;

architecture TBRAM of TB_RAM1 is
 signal RD1,WR1,LOW_CS1 : BIT;
 signal DATA_IN1, DATA_OUT1 : BIT_VECTOR ( 3 downto 0);
 signal ADDRESS1 : BIT_VECTOR ( 4 downto 0);
 signal RES,DT1, DT2 : BIT_VECTOR ( 3 downto 0);


component RAM_D
  generic ( RDEL, DISDEL : TIME );
  port ( DATA_IN : in BIT_VECTOR ( 3 downto 0);
         DATA_OUT : out BIT_VECTOR (3 downto 0);
          ADDRESS : in BIT_VECTOR (4 downto 0) ;
          RD,WR, LOW_CS : in BIT );
end component;

for L1 : RAM_D use entity RAM1 (RAM_ALG);

begin
      L1 : RAM_D
      generic map ( 5 ns, 5 ns )
      port map  ( DATA_IN1,DATA_OUT1, ADDRESS1,RD1,  WR1, LOW_CS1);


     CS_RAM : process
              begin
                 LOW_CS1 <= '1' after 2 ns, '0' after 5 ns ,
                            '1' after 180 ns, 
                            '0' after 185 ns, '1' after 220 ns;
                 wait;
     end process CS_RAM;
     WRITE_RAM : process
              begin   
                 WR1 <= '1' after 10 ns, '0' after 160 ns;
                 wait;
     end process WRITE_RAM;

      --  ADDR_DAT : process
             --   begin
                  DATA_IN1 <=  "1111" after 10 ns, "1110" after 20 ns,
                              "1101" after 30 ns, "1100" after 40 ns,
                              "1011" after 50 ns, "1010" after 60 ns,
                              "1001" after 70 ns, "1000" after 80 ns,
                              "0111" after 90 ns, "0110" after 100 ns,
                              "0101" after 110 ns, "0100" after 120 ns,
                              "0011" after 130 ns, "0010" after 140 ns,
                              "0001" after 150 ns;



                  ADDRESS1 <= "00001" after 10 ns, "00010" after 20 ns,
                              "00011" after 30 ns, "00100" after 40 ns,
                              "00101" after 50 ns, "00110" after 60 ns,
                              "00111" after 70 ns, "01000" after 80 ns,
                              "01001" after 90 ns, "01010" after 100 ns,
                              "01011" after 110 ns, "01100" after 120 ns,
                              "01101" after 130 ns, "01110" after 140 ns,
                              "01111" after 150 ns, 
                              "01011" after 190 ns, "01010" after 210 ns;

                --  ADDRESS1 <= "01011" after 190 ns, "01010" after 200 ns;
               --   wait;
  --  end process ADDR_DAT;

                 
  READ_RAM: process 
          begin
                 RD1 <= '1' after 190 ns, 
                         '0' after 215 ns;
                 wait;
  end process READ_RAM;

  AND_RAM_LOC: process ( RD1, ADDRESS1 )
               begin 
                    if (RD1 = '1') and (ADDRESS1 = "01011") then 
                          DT1 <= DATA_OUT1 after 5 ns ; 
                        end if;
                    if (RD1 = '1') and (ADDRESS1 = "01010") then
                        DT2 <=  DATA_OUT1 after 5 ns; end if;
                   
                    RES <= DT1 and DT2;
                end process AND_RAM_LOC;
                  

end TBRAM;