D. Nikonov, G. Csaba, W. Porod, T. Shibata, D. Voils, D., Hammerstrom, I. Young, and G. Bourianoff,
"Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition," IEEE Journal on
Exploratory Solid-State Computational Devices and Circuits, Vol. 1, pp. 85-93, 2015.
M.S. Zaveri, D. Hammerstrom, "Performance/price estimates for cortex-scale hardware: A design
space exploration," Neural Networks, (Archival Journal of the International Neural Network Society),
Elsevier, April, 2011, Pages: 291-304, DOI:10.1016/j.neunet.2010.12.003.
Mazad S. Zaveri and Dan Hammerstrom, “Nano/CMOS implementations of Inference in Bayesian
Memory – An Architecture Assessment Methodology,” IEEE Transactions on Nanotechnology, Vol. 9,
No. 2, March 2010, pp. 194-211.
A. Mathuria, D.W. Hammerstrom, "Approximate Pattern Matching using Hierarchical Graph
Construction and Sparse Distributed Representation," International Conference on Neuromorphic
Systems, Knoxville, TN, July 23-5, 2019.
Kamela C. Rahman, Dan Hammerstrom, Yiwei Li, Hongyan Castagnaro, and Marek A. Perkowski,
“Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic based
Reconfigurable Architecture”, IEEE Transactions on Nano-technology, Volume: 15, Issue: 4, July
2016.