Michael Levy


Introduction:

This document discusses my ECE 271 project. There are ***5*** sections that follow. The first section is the abstract for my project. The abstract outlines the current rules that a PSM (probabilistic state machine) will follow during its operation. After the abstraction was completed, I undertook to design a circuit that would operate according to the PSM rules. I used Mentor Graphics Tools to design and simulate one such realization. The Mentor design uses low level gates such as AND, OR, NAND and NOR. In order to physically build this PSM I did not want to deal with many low-level gates. In fact, I did not want to deal with any low-level gates. I decided to implement the bulk of my design with GAL's (gate array logic). An intermediate step, necessary for full implementation, would be to write VHDL (very high density logic????) code.

I wrote three VHDL codes for the three GAL's that were needed. VHDL is an excellent tool for my application. With VHDL, I could write a program in terms of combinational logic, sequential logic, or a mixture of the two?????. The third section of this document describes how I transposed my Mentor circuit into a circuit comprised of three GAL's by using VHDL code. In the fourth section I compare simulation results with actual results. The simulation results were obtained in a two step process. The first step entailed compiling my VHDL code with 'Galaxy'??. This produced a JEDEC (*.jed) file. The Actual simulation was done using NOVA simulator. NOVA requires JEDEC file as well as sets of test vectors with which to simulate. Simulation results were grabbed using XV. As previously stated, these results were used to verify actual results obtained using a logic analyzer. All important functions were checked in this way, to ensure success.


Abstract:

The central themes of the Probabilistic State Machine (PSM) are highlighted by the following rules.

  1. There are 4 unique input vectors that the system recognizes.

  2. There are 4 unique output vectors of the system.

  3. There is not a one to one relationship between an input and an output. Meaning that input A does not necessarily cause output A to be in an active state.

  4. Each input must cause one of the four output vectors to an active state.

  5. The probability of an output vector (in an active state), is a function of the given input vector. So for each input vector there may exist different probabilities for the occurrences of a given output vector.

  6. Each input vector may be associated with a unique probability distribution of the output vectors.

  7. For each input, the sum of all probabilities of all outputs must equal one.

    Input vector

    Output vector 1 Probability

    Output vector 2 Probability

    Output vector 3 Probability

    Output vector 4 Probability

    1

    a11 / 100

    a12 / 100

    a13 / 100

    a14 / 100

    2

    a21 / 100

    a22 / 100

    a23 / 100

    a24 / 100

    3

    a31 / 100

    a33 / 100

    a33 / 100

    a34 / 100

    4

    a41 / 100

    a42 / 100

    a43 / 100

    a44 / 100

    Where a11 + a 12 + a13 + a14 = 100, and

        a21 + a 22 + a23 + a24 = 100, and

        a31 + a 32 + a33 + a34 = 100, and

        a41 + a 42 + a43 + a44 = 100.

    ought that each input vector will place does not correspond directly to one sequence of outputs, rather, it guides the machine to choice its output via a probability distribution function.

The probabilistic state machine (PSM) is based upon several day dreams that I have been having recently. Ultimately, I would like to create a simple architecture capable of adjusting itself to it's environment. In order to realize this, the architecture must have freedom to alter its input-output behavior through time.


Mentor PSM Circuit Development:

In order to formalize the abstract of the PSM into a viable circuit, I used Mentor Graphics tools. With Mentors help, I was able to design and simulate all the data paths. My Mentor circuit consists of five main modules, a two-bit input signal, and a four-bit one-hot code output signal. The five modules include: an 8-bit shift register, an array of OR gates, 4 parallel multiplexers, and two logic circuits for create excitation functions. A brief description of the modules follows.

The 8 bit registry is a cyclic shift register. I intend for only one of its bits to be in an active state (logical high) at a given time. All the 'clears' are held high, and the 'preset' is started low and switched to high (This is eventually implemented via a mechanically switch.). A debouncer circuit will be included on the preset line in order nullify erratic switching effects. After the preset is pulled high, all the flip- flops are low (logical low). In order for one of the eight flip- flop outputs to become high, I have added a pulse generator. The generator is an asynchronous device. It asserts a high onto one of the flip-flop inputs whenever all flip- flop outputs are low. These two modules cooperate to ensure that there is one and only one high output in the registry. Consequently, the probability that a bit in the registry is in an active state is 1:8.

Another important module is the pulse excitation. By using a multiplexer, this module actually turns the first register into a generalized register. The first register will either load the output of the last register or it will load a high pulse. What is loaded depends on the outputs of the registry. If all the registry outputs are low, then a high is loaded to register one. If at least one of the registry outputs is high then the output from the last register is loaded. If there is no pulse on the registry the multiplexer passes data from Vcc, or else it allows data to pass cyclically.

Now we have established a system having one and only hot (logical high) output on its registry. With this information we can begin to add this base probability (1:8) to form various probability distributions on the PSM. For example, if we were to connect all the lines of the registry into an 8-input 'OR' gate, and then feed the 'OR' gate output directly to output '1' of the PSM, then PSM output '1' would immutably remain high. In general, the 'OR' array distributes the probability from the registry to the outputs. As stated in the abstract two rules must always be followed though. First, each registry wire may only affect change in one output at any given time (i.e. registry line 2 can not be connected to output 1 and two at the same time). Second all eight registry outputs must be physically connected to one output or another at every clock pulse.

In the abstract it is stated that the probability distributions of the output vectors should be influenced by the input vector. This is accomplished by using four multiplexers in parallel with each other. In my schematic it is not clear that there are four multiplexers, but, there are. While glancing at the 4*MUX you will see 4 groupings of 4 gates. (Each group has four gates). We can label each gate with a group number and a number which represents which gate in the group it is (starting form the left. There is gate <1,1>, <1,2>, <1,3>, <1,4>, <2,1>, <2,2>, <2,3><2,4>,..., <4,3>, and <4,4>. Each input will allow data to pass through 4 of the gates while preventing data to pass through the other twelve. For example, if input one and input two are both low, then gates <1,4>, <2,4>, <3,4>, and <4,4> will be able to transmit data. Meanwhile, from previous discussion, only one of these gates can be high at a time. Consequently at a given time only one high pulse is able to exit the 4*MUX. The pulse that gets through will act as an enabling signal for one of four behaviors (actions ideas decisions etc.). the four multiplexers allow four independent probability distributions. Each two-bit input (In1 and In2) selects a different probability spectrum. If there is confusion at this point, please refer to the schematics and re-read this document.

As the circuit has been explained so far it should be understood that the the output vector is, in most instances, changing in time. The last module to be covered, the output enable function, is used to hold an output vector steady. The current design will only allow a change of the output vector when one of the two inputs is changed. This is accomplished by placing attaching each input to the input of a D flip flop. If the input changes this will not register on the output until the next rising clock. These disparities of the inputs and outputs of a flip flop trigger the output enable. Enable = (D1 XOR Q1) OR (D2 XOR Q2). The output will be enabled from the moment that one of the inputs change until the shortly after the next rising clock.

The output enable function works in concert with the final output registers. The clock input of the PSM output registers are not connected directly to the clock signal. Rather, the clock signal is ANDed with the output enable function. In this way, the PSM output registers are not clocked unless the clock signal and the output enable signal go high.

*INSERT TABLE**

VHDL Implementation:

It would be absurd to realize the Mentor circuit with small gates and a solder. The same functions could be implemented on GAL's. VHDL code can create source files with which to program GAL's. So I wrote all the necessary code to implement the PSM. (Actually i modified existing code to suit my particular needs.) The procedure is as follows. First create the VHDL code with a text editor. Galaxy, a Cypress Tools product is then used to compile the code. We test the source code with the NOVA simulator. If the code is correct we create a fuse map to burn the GAL's.

As previously mentioned I burned three distinct GALS. I used GAL16v8 compatible chips. Three chips were needed because of the amount of expressions (laterals) that were required. For the most part each of the **X** modules previously discussed are implemented on separate GAL's. When ever possible, I incorporated more than one module on the same chip. There are only 18 pins to work with on the chip and depending upon the exact function required, several pins may need to be reserved for the logic. The following list can be used to see how the modules spoken of above fit into each GAL.

hot_out.vhd realizes the 'OR' topology for the various probability spectrums

mod2_out realizes the 'output enable function' and also converts the four bit output from 'MUX*4' into a two pin output. This last function is not necessary to implement the PSM, but, it may make it easier to connect to another system.

prob_gen.vhd realizes the 'pulse excitation' and the 'registry' modules.


Result Verification:

After compiling the VHDL codes, I was able to set up test vectors on various inputs and check to be sure that all the correct functionality was present. I saved these simulations as plots. They were compared with data from my circuit that I acquired with a logic analyzer. I did not test every possibility, rather, I only checked the various outputs with inputs that I knew would occur.

comparison of all waveforms relating to hot_out.vhd

comparison of all waveforms relating to mod2_out.vhd

comparison of all waveforms relating to prob_gen.vhd

As shown in the previous diagrams, all the functionality that is required for the PSM had been realized.


Conclusion:

The initial purpose of the Probabalistic State Machine was to model a behavioral model for simple organism. In this case, one that can react to 4 stimuli in any of 4 manners. As is often the case when dealing with organisms, one stimuli does not correspond one to one with a particular action. In my view, the PSM can be used as an engine to drive robots and moving sculptures in a way that is not 100 percent predictable. I view this version of the PSM to be incomplete.

In this project, the exact probabilities distribution are static and known. In future ventures, these probabilities will be dynamic and, most probably, unknown. The upshot of this work has brought me closer to realizing circuitry for adaptive learning systems. I now have a physical model for an circuit that may, with feedback, may coordinate different actions to achieve certain tasks. For example, what if the OR array, could be manipulated on the fly with the aid of a feed back network. In this case it may be able to modify its responses when they have proven to be unfruitful.


Glossary of Terms:

PSM

GAL

NOVA GALAXY XV

one-hot

generalized register