Simulation: Flip flop outputs (in1plus and in2plus) follow inputs on rising clock edge only when reset is low
Waveforms Pertaining to mod2_out.vhd
On my circuit, output 'in1plus' is shorted to input 'dummy1'. A similar situation exist for 'in2plus'. The enable output can be ANDed with
clock signal at the inputs of the output registers. In this case, the final PSM outputs will only change when there is a change in the input stimuli.
Simulation:
Flip flop outputs (in1plus and in2plus) follow inputs on rising
clock edge only when reset is low
Data:
Flip flop outputs follow flip flop inputs on rising clock (TST06)
edge
Simulation:
asynchronous en_out = (in1 XOR dummy1) OR (in2 XOR dummy2)
Data:
asynchronous ENABL = (IN1 XOR IN1_+) OR (IN2 XOR IN2_+)
If necessary, the 4 bit output vector can be cnverted to a 2 bit vector. This is done with OR gates. See VHDL code 'mod2_out.vhd' for details.
Simulation:
Conversion of a 4 bit to a 2 bit PSM output vector
Data:
PSM_1 = HOT_0 OR HOT_1, PSM_2 = HOT_1 OR HOT_2