Schedule of EE 271
- LECTURE 1: Monday, June 19.
Short Introduction and about this class, projects.
Truth Tables versus expressions versus Karnaugh Maps.
Short review of minterms, prime implicants, essential prime
implicants, K-map minimizaton of boolean fuctnions of single-output
and multi-output functions.
Extended review of K-maps for arbitrary number of variables and their use for minimization.
The concept of verification by reduction to canonical forms.
Various technologies and families of gates.
Robots at PSU and robotics projects.
- LECTURE 2: Wednesday, June 21.
Introduction to projects.
- Fundamentals of robotics
- Machine Learning in robotics
- Our robots: spiders, arms, heads and MUVAL.
- Robots in labyrinths. Sensors and behaviors.
- Robotic Projects Ideas Solicitation: "What is that you want to do?"
- Importance of practicality and creativity. How to work on projects.
- Finite State Machines to control robots.
- Shifters and Johnson counters.
- Hierarchical FSM with ROMs and controller for a spider robot.
Reading Assignment Review chapters 1 - 6 from Roth. Do as many problems as necessary
to become fluent, find solutions in the Roth book.
- RECITATION 1: Friday, June 23.
Remember that this meeting is voluntary and no new material is covered.
- Review of Karnaugh Maps: variables,
literals, products, product implicants, Prime implicants, essential prime implicants.
- How to draw a Kmap.
- Finding good groups in a Kmap.
- Covering problem.
- Mathematical Method to solve the covering problem: Petrick function.
- Review of Shifters.
- Analysis of autonomous FSM.
- Analysis of non-autonomous FSM: from schematic to state machine graph.
- LECTURE 3: Monday, June 26.
Various uses of Kmaps to design with Muxes.
Analysis methods (based on Kmaps, netlists, expressions).
The importance of good selection of the analysis method.
The relations between analysis and synthesis.
NAND and NOR gates. Their use.
Latches - review. Material from chapter 11 from Roth.
Flip-Flops - review. Material from chapter 11 from Roth.
Synchronous Devices.
Designing binary counters.
Designing sequential parity checkers.
Review of sequential parity checkers.
The notations used for state machines.
Moore and Mealy machines, examples.
Review of the basic method to calculate the excitation functions for Mealy machines.
Timing analysis of Mealy machine.
Schematics of Finite State Machines and their analysis.
FSMs as sequence transformers, acceptors and generators, time analysis.
Reading Assignment Review chapters 7 - 13 from Roth. (Chapters 1-6 were
assigned earlier). Do as many problems as necessary
to become fluent, find solutions in the Roth book.
Review also (optional) the corresponding materials in Doug Hall's book.
Writing Assignment Create your WWW Page for ECE 271.
Write what is your project and what are your project ideas. Be very specific,
what you want to do, how, cost, software, design, etc.
It is enough if every group will have a common project proposal, but everybody has to set a
WWW Page for himself.
You can use HTML or Netscape or any tool to create your WWW Page.
It should have your name, your photo, info abou you that you want to share,
classes that you have taken and interest. Look to previous WWW Pages of students in this class.
I believe you can do even better pages.
If you have troubles to create the WWW Page, give me your description on paper.
MONDAY, JULY 3.
MONDAY, JULY 10.
- LECTURE 3: Wednesday June 28.
Complete sets of gates, examples: NAND, NOR, AND/OR/NOT, AND/EXOR/1.
Incompletely specified functions.
Simple methods of EXOR-based synthesis by Kmap methods.
Factorization of multi-output functions.
Inhibition methods that use NAND and NOR gates.
Combining various logic synthesis methods together.
Most of this material is in chapters 1-10 of Roth book. Some is in Doug Hall's book.
All will be in my book that I will give to you in few days.
Reading Assignment Review chapters 7 - 13 from Roth. Do as many problems as necessary
to become fluent, find solutions in the Roth book.
Review also (optional) the corresponding materials in Doug Hall's book.
- LECTURE 4: Monday July 3.
Short review of minterms, prime implicants, essential prime
implicants, K-map minimizaton of boolean fuctnions of single-output
and multi-output functions.
One example of a multi-output functions minimized separately and
then using shared terms. Comparison of cost of these two ways of minimization.
The concept of PLA, the function from the previous example represented as a PLA.
Espresso format, the outline of Espresso procedure of minimization.
MUXes (as selectors), deMUXes (as decoders). Cascading decoders.
Incomplete decoders. Everything in gate-level schematics.
The number of boolean functions for n-variables. Complete system
of operations. Proof for {1,AND,EXOR}
Implementation using NAND and NOR. The rule of the thumb,
POS->NOR, SOP->NAND.
Two major examples from the book of mapping multi-output
functions using NAND and NOR.
Reading Assignment Review chapters 7 - 13 from Roth. Do as many problems as necessary
to become fluent, find solutions in the Roth book.
Review also (optional) the corresponding materials in Doug Hall's book.
- LECTURE 5: Wednesday July 5.
(Unexpected, hehe) Quizz 1.
This quizz will test your knowledge of EE 171 and the repetition material
covered in the first two weeks of the class.
Chapters 1 to 13 (inclusive) from the Roth book will be covered.
This seems like a lot, but I remind that this is all a review.
The quizz is "open book". Bring all your creepsheets.
Assignment of Homework 1: Create your own WWW Page. Due next Wednesday.
Send me an email with your page address.
Write about your interests related to this class.
If you have already a WWW Page, show on it clearly which part is related to this class.
Find information on Oregon High tech companies and put to your WWW Page.
Designing with one large MUX.
Designing with MUX and gates. Expanding functions with respect to subsets of variables.
Various patters of control variables on a Kmap.
Use of MUXes for hierarchical decomposition.
D flip-flops.
Combining various logic synthesis methods.
Iterative circuits: carry in one or in two directions.
The need for verification. Verification methods: graphical versus symbolic.
More info on FFs.
Shift registers and Johnson Counters.
Generalized registers based on D ffs and MUX.
Generalized registers with non-bit-wise operations.
READING ASSIGNMENT: Roth Book Chapters 1 - 14 from Roth, most is review.
Concentrate especially on topics that we covered in the class and in the "unexpected" quizz.
- LECTURE 6: Monday July 10.
Reading Assignment: Read chapter 15 from Roth.
Solve three arbitrary problems that have solutions and check them.
Design of counters with large sequences.
Systematic Procedures for designing state machines with D, T and JK flip-flops.
Method with bold symbols. Selection of the best flip-flop.
Designing a flip-flop from another flip-flop.
Review on generalized registers: combining generalized registers with counters and adders.
Systematic versus ad hoc methods for designing state machines.
K-Map type of problems, versus Generalized Register type of problems.
Design of sequence acceptors and sequence generators.
Iterative Circuits. Addition, comparison,
Iterative circuits. Use of State Tables for Iterative Logic - repetition.
Register transfer using Shift registers.
Arithmetic and logic operations using Shift registers.
Relations between state machines and iterative circuits.
- LECTURE 7: Wednesday July 12.
- This class will be taught by Anas Al-Rabadi. I am in California attending
the Second NASA/DOD Conference on Evolvable Hardware and visiting robotics companies.
- Quizz 2.
Reading Assignment: Review in detail chapter 15 from Roth.
Concentrate on two topics: State Machine Minimization, and State Machine Assignment.
Reading Assignment: Read chapters 16 and 17 from Roth.
On programmable logic: here
Lecture: Equivalent States and Equivalent State Machines.
State Minimization.
State Assignment. Fast procedures.
Use of Flip-flops in state machine design - repetition.
Please review our previous examples of iterative circuits and state machines designed from tables:
adder, bit-by-bit operations, comparator of order, comparator of equality, sequence detectors,
iterative circuit to find maximum of n K-bit numbers,
iterative circuit with carry going in two directions to find the first and the last "one" in a string.
I treat iterative circuits as a very important component of this class and therefore
I teach and review them so many times.
It is very problable that they will be in the midterm.
Definitely, they will be a subject of the final.
Assignment: Read chapters 11 to 15 from Roth book.
- LECTURE 8: Monday July 17.
READING ASSIGNMENT FOR NEXT WEEK: chapters 18 and 19 from Roth.
MIDTERM, OPEN BOOK.
This midterm will be 3 hours, and it will include whole material from chapters 1 to 17 from Roth book.
There will be 3 to 4 problems to solve. Open Book.
All problems will be taken from Roth's Book, chapter 1 - 17.
- LECTURE 9: Wednesday July 19.
Much of these readings is a repetition.
This class will be mostly solving problems from midterm and repetition.
- LECTURE 10: Monday July 24.
The lecture will cover Chapters 18, 19, 20, 21, and their extensions.
Observe, that we already covered much of this material in our discussion on
serial versus parallel and sequential versus combinational operations.
Data Path Design for Microprocessors.
- LECTURE 11: Wednesday July 26.
Asynchronous Finite State Machines.
READING ASSIGNMENT: chapters 22, 23, 24 and 25.
- LECTURE 12: Monday July 31.
System Level Design. Multiplication, division. Review chapters 18-21.
Memory.
VHDL.
Typical descriptions in VHDL. Look to my other classes, especially VHDL class,
for examples of projects.
Your VHDL projects in this class, are however, much simpler.
If you feel that you need review of VHDL, look to the VHDL tutorials, and to my VHDL WWW Page.
- LECTURE 13: Wednesday August 2.
Microprocessors and microcomputers. Memory organization.
READING ASSIGNMENT: chapters 26 and 27.
- LECTURE 14: Monday August 7.
Test and design for test.
Materials about Test and Design for Testability
Test text
Figure on test equivalence
Data Path and computer architectures.
Good tutorial
Lectures and slides on
Computer Architecture, good material
I will accept project descriptions until Tuesday, August 8, 10 a.m. morning.
See elsewhere on this WWW Page for the format of project description.
You must document that the project works (both hardware and software).
- LECTURE 15: Wednesday August 9.
This will be a comprehensive exam that will include the entire class material,
except VHDL and projects.
In particular, the material from all quizzes, homeworks, and the midterm.
OPEN BOOK. The duration of the exam will be 4.5
hours, so nobody would complain about the lack of time.
GOOD LUCK. !!
Have a good vacation.
Check your grades on the door of my room or in ECE office, room 102.
Syllabus of EE 271