INSTRUCTOR: Marek Perkowski
Portland State University, Department of Electrical Engineering

Course Content Guide

Marek A. Perkowski,
Professor of Electrical Engineering Department
Portland State University
Portland, OR 97207-0751


The approach here is to use shift register counters as 
a review of state machine analysis and use the hang state problem 
to lead into custom state-machine design with discrete flip-
flops, PALs, and latches. Computer based simulation is used to 
verify the state sequence and the timing of state machine 
designs. The discussion of latch based state machines leads 
easily to an introduction to LSSD and boundary scan test 
techniques. This plants the idea that designs should be testable.

The rest of the course is a bottom-up approach to the 
circuitry used inside a microprocessor and to the devices and 
circuitry used in a basic microcomputer system. Discussions of 
arithmetic techniques and devices lead into the architecture and 
internal operation of a simple microprocessor. The bus cycle 
operation of the microprocessor is then discussed. Finally, 
memory devices and systems are discussed. The logic and timing of 
a various state machine designs are tested with computer based 
simulation. This course reinforces design methodology, 
documentation standards, and use of computer based tools 
introduced in EE171.


Digital Systems Design is the second course in a sequence of 
digital and microprocessor courses. This course covers shift 
register devices and circuits; design and application of 
state machine circuits using discrete devices and 
programmable logic devices; arithmetic circuits and devices; 
internal architecture of a microprocessor; design and 
interfacing of memory systems, and an introduction to design 
for test techniques.
  • Digital Systems Design is a 4-credit course that meets 4- lecture hours per week.


    Course activities will include lecture presentations, 
    coordinated homework assignments, two or more design projects, and 
    examinations which monitor student progress in meeting course 

    Additional recitations and supervised problem-solving sessions.


    The student enrolling in EE271 must have successfully completed EE171.


    1.1.0. Sum of Product Circuits (SOP). Prime implicants (groups of ones), essential primes.
    1.1.1. Product of Sums Circuits (POS). Prime implicates (groups of zeros).
    1.1.2. Realizations of SOP and POS circuits with NAND and NOR gates.
    1.1.3. Use of EXOR and EQUIVALENCE gates in synthesis.
    1.1.4. Use of factorization and de Morgan rules.
    1.1.5. Analysis of combinational circuits.


    Instructional Goal: To study the operation, design, and applications of shift register circuits.
    2.1.0. SSI Shift Registers
    2.1.1. Draw the schematic diagram for a shift register using discrete flip-flops.
    2.1.2. Analyze and draw a state diagram for specified shift register counters such as twisted ring.
    2.1.3. Determine hang state(s) for circuits such as a Linear Feedback Shift Register
    2.1.4. Design a shift register circuit which produces a specified waveform sequence when clocked.
    2.1.5. Johnson Counter and shift registers as counters.
    2.1.6. Design of multiplexer-based registers that implement arbitrary subset of the following operations: shift left, shift right, shift cyclically left, shift cyclically right, parallel read-in, parallel read-out, complementation of the contents, preservation of the contents,

    2.2.0. MSI Shift Registers.
    2.2.1. Read and interpret the data sheet for MSI shift register circuits.
    2.2.2. Describe the operation and timing of systems using shift registers.


    3.1.0. Period, up/down counting and code of the counter.
    3.1.1. Counters with output logic and counters in which state signals are output signals.
    3.1.2. Design of exemplary counters.


    Instructional Goal: To learn how to design a variety of synchronous state machines.
    4.1.1. Designing State Machines with Discrete Flip-flops.
    4.1.2. Draw a block diagram for a Mealy type state machine and describe its operation.
    4.1.3. Draw a block diagram for a Moore type state machine and describe its operation.
    4.1.4. Given a problem statement, draw a state diagram or an ASM chart for the problem.
    4.1.5. Draw a next state table which describes the desired state transitions.
    4.1.6. Make state assignments which attempt to minimize the number of variables which change during state transitions.
    4.1.7. Decide on the type of flip-flop and write an excitation table for the design.
    4.1.8. Use Karnaugh maps or some other technique to simplify the next-state decoder logic.
    4.1.9. Choose a logic family which is fast enough to work at the desired clock frequency.
    4.1.10. Draw the schematic for the flip-flops and next-state-decoder.
    4.1.11. Simplify and implement the output decoder.
    4.1.12. Simulate the completed design to verify that the state sequence is correct and that there are no timing problems.
    4.1.13. Calculate the maximum frequency of operation for a state machine and verify the computation with a simulator.

    4.2.0. Using VHDL to Implementing State Machines in PALs.
    4.2.1. Design the algorithm for a specified state machine.
    4.2.2. Translate the algorithm into an RTL model or structural model described in VHDL.
    4.2.3. Implement models with synchronous or asynchronous control signals such as preset or clear.
    4.2.4. Use a tool such as Cypress WARP2+ to create a fusemap (JEDEC) file from the VHDL description.
    4.2.5. Simultate the JEDEC file to verify its correct operation.
    4.2.6. Develop test vectors for the PAL design.
    4.2.7. Integrate a PAL state machine into a schematic based design which can be simulated with the Mentor Graphics QuickSimII simulator.


    Instructional Goal: To become familiar with some of the techniques used to make digital circuits testable.

    5.1.0. Combinational Circuit Tests.
    5.1.1. Describe the testing problem caused by redundant logic in combinational logic circuits.
    5.1.2. Describe how a combinational logic circuit can be made more testable by path sensitization.
    5.2.0. Sequential Circuit Tests
    5.2.1. Design a simple two-phase latch state machine.
    5.2.2. Describe how test patterns can be shifted in and test results shifted out of a state machine built with Level Sensitive Scan Design(LSSD) cells.
    5.2.3. Describe how IEEE 1149.1 Boundary Scan is implemented in Digital ICs.
    5.2.4. Describe how Pseudo Random Number Generators are used for test generation in Built-In-Self-Test(BIST) circuitry.
    5.2.5. Describe the operation of a Linear Feedback Shift Register and explain how it is used for data compression in BIST.


    Instructional goal: To become familiar with the operation and timing of asynchronous state machines.

    6.0.1. Break the feedback loop(s) in an asynchronous state machine circuit so the sequence can be analyzed.
    6.0.2. Draw a transition state table for an Asynchronous State Machine.
    6.0.3. Draw a flow table for an Asynchronous State Machine.
    6.0.4. Identify non-critical race, critical race, hazard and instability conditions in an Asynchronous State Machine.


    Instructional Goals: To become familiar with performing basic arithmetic operations on numbers in different number systems and to become familiar with the hardware used to perform arithmetic and logic operations on binary numbers.

    7.1.0. Arithmetic Techniques.
    7.1.1. Add, subtract, multiply, and divide binary numbers.
    7.1.2. Convert negative integer numbers to and from their two's complement sign and magnitude representation.
    7.1.3. Add and subtract BCD, octal, and hexadecimal numbers.
    7.2.0. Arithmetic Devices and Circuits.
    7.2.1. Describe the operation of a 4-bit full adder device.
    7.2.2. Describe the operation of a magnitude comparator device.
    7.2.3. Predict the results produced by ANDing, ORing, and EXORing two specified binary words with an ALU
    7.2.4. Use the data sheet to determine the programming required on the select inputs of an ALU to cause it to perform a specified function.


    Instructional Goal: To show how an ALU can be combined with registers and other circuitry to form a microprocessor.

    8.1.0. Describe the basic structure and operation of a bit-slice microprocessor.
    8.1.1. Define the terms microprogram ROM, pipeline register, sequencer, and control logic.
    8.1.2. Draw a block diagram showing how these elements can be connected with an ALU and some registers to form a basic microprocessor.
    8.1.3. Describe the sequence of actions that occur as the microprocessor described in 6.1.2 executes an instruction.


    Instructional Goal: To develop an awareness of the major components of a basic microcomputer system and the typical bus activities that occur as the microcomputer fetches and executes instructions.

    9.1.0. Microcomputer Components.
    9.1.1. Draw a block diagram of a simple microcomputer showing buses, CPU, memory, and ports.
    9.1.2. Describe the sequence of actions that a microprocessor will carry out as it fetches and executes an instruction.
    9.1.3. Explain the purposes of data bus transceivers in a microcomputer system.
    9.2.0. Microcomputer Timing Introduction.
    9.2.1. Given a timing diagram, describe the sequence of signals that occur on the buses as the microprocessor reads a data word from memory.
    9.2.2. Given a timing diagram, describe the sequence of signals that occur on the buses as the microprocessor writes a data word to memory.
    9.2.3. Define the term "wait state" and explain why wait states are often inserted in microcomputer bus cycles.


    Instructional Goal: to develop knowledge of the different types of memory devices commonly used in a microcomputer.

    10.1.0. ROM type Memories.
    10.1.1. Define the following acronyms: ROM, PROM, EPROM, EEPROM, Flash EPROM.
    10.1.2. Define what a specification such as "32K x 8" means when referring to memory devices.
    10.1.3. Define the terms "address access time", "chip select access time", and "output enable access time".
    10.2.0. Static RAM.
    10.2.1. Describe how data bits are stored in static RAMs.
    10.2.2. From a data sheet determine the read and write access times for a static RAM.
    10.3.0. Dynamic RAM.
    10.3.1. Describe how data bits are stored in dynamic RAMS.
    10.3.2. Given a timing diagram for a dynamic RAM describe the sequence of signals required to read data from the device and the sequence of signals required to write data to the device.
    10.3.3. Explain why the read cycle time for a DRAM is considerably longer than the access time.
    10.3.4. Describe how a DRAM is refreshed using the RAS only method.
    10.3.5. Explain the difference between distributed refresh and burst refresh modes.


    Instructional Goal: To learn how memory devices are connected in microcomputer systems and how a desired memory or I/O device is selected for access.

    11.1.0. Address Decoding.
    11.1.1. Draw a diagram showing how address, data and control lines are connected to a bank of static RAMs or ROMs.
    11.1.2. Define the terms "memory mapped I/O" and "direct I/O."
    11.1.3. Describe how an address decoder selects a desired device in a system.
    11.1.4. Design simple address decoders for a variety of memory and I/O configurations.
    11.2.0. Memory Timing.
    11.2.1. For a specified design compute the time between an address being sent out from the microprocessor and data returning from memory to the microprocessor.
    11.2.2. Determine if a bank of memory devices are fast enough to operate without wait states in a simple system.
    11.3.0. DRAM Memory Systems.
    11.3.1. Describe how a DRAM refresh controller IC manages an array of dynamic RAMs.
    11.3.2. Describe how errors are detected in data read from an array of dynamic RAMs using the parity method.
    11.3.4. Describe in general terms how an SRAM cache is used to reduce the average number of wait states required for DRAM.


    Instructional Goal: To help students develop a systematic approach to a design projects.

    12.1.0. Documentation.
    12.1.1. Thoroughly document the development of a combinational logic design project such as a 6-input 3-output circuit built with discrete SSI devices.
    12.1.2. Keep an "as you go" design log showing all preliminary thinking, design steps, simulation results, etc.
    12.2.0. Design Process Steps.
    12.2.1. Carefully define a given design project.
    12.2.2. Draw a block diagram showing input and output signals.
    12.2.3. Write an algorithm for the relationships between input signals and the desired sequence of states.
    12.2.4. Write a truth table for the output decoder.
    12.2.5. Use Karnaugh maps or some other technique to minimize the Next State Decoder and the Output Decoder.
    12.2.6. Draw the schematic for the circuit.
    12.2.7. Simulate the circuit to verify that it sequences
    correctly and has no timing problems.


    Instructional Goal: To gain more skill with the computer based tools currently used for digital design.

    13.1.0. Schematic Capture and Simulation.
    13.1.1. Use a schematic capture program such as Mentor Graphics Design Architect to draw schematics for sequential logic circuits.
    13.1.2. Prepare a schematic design file for simulation by running a Design Rule Check and an Electrical Rule Check.
    13.1.3. Generate the stimulus file for the simulation.
    13.1.4. Run a simulation with a simulator such as Mentor Graphics QuickSimII to determine if the sequence for the circuit is correct and if the timing for the circuit is correct.
    13.2.0. VHDL Design and Simulation.
    13.2.1. Write a VHDL description for a synchronous state machine circuit and use a PAL Development program such as
    Cypress Semiconductor's Warp 2+ to generate the JEDEC file.
    13.2.2. Simulate the JEDEC file to verify its operation.
    13.2.3. Use a simulator such as Mentor's QuickSimII to link the JEDECs files to schematic based models and simulate the resultant design.


    14.1.0. Causes and Characteristics of Metastability.
    14.1.1. Describe what is meant by a metastable output.
    14.1.2. Describe the major cause of metastability.
    14.2.0. Synchronizers.
    14.2.1. Draw a circuit for a D Flip-flop synchronizer.
    14.2.2. Describe some common methods for improving the
    Mean Time Between Failure (MTBF) for a synchronizer.