PLAs are used in many design to realize the logic part of FSMs or blocks of combinational functions. If not minimized, PLAs can become extremely large, consume a lot of power and are slow. For PLA design the problems of Boolean minimization partitioning and folding are addressed. Logic minimization consists of minimization of numbers of terms and sometimes also number of literals in terms (for less power consumption, reliability and foldability). The Boolean minimization algorithms for PLAs are optimum or approximate. The first can be used for not more than 14 variables in general case and up to 20 variables for most industrial functions [42]. The commonly used approximate program, Espresso, [23] introduced a number of new theoretical and implementation ideas that are now being tuned and improved both in industry and in universities. The topological optimization includes partitioning [104], and folding (Hachtel) to decrease the area of unused space inside a PLA. Folding attempts to find such a permutation of rows and/or columns of AND and OR planes in the PLA, that as many as possible rows or columns can be combined (folded) into single rows or columns. Various folded architectures and folding algorithms have been implemented in UC Berkeley, IBM and other places. Topological partitioning methods are described in [52]. Recently the simulating annealing method [111] has been used by several authors as a general method of solving combinatorial problems in CAD, including all problems related to PLA optimization as well as many problems related to multilevel optimization. The important partial problems related to (mostly) two-level synthesis are that of complementation of a Boolean function [156], and recognizing and minimizing unate functions [9, 24] (unate function is a sum of products of non-negated variables).
Since operations on arrays of cubes representing Boolean functions are relatively slow and are repeatedly used in the design process, hardware accelerators for them have been recently proposed. Sasao had constructed a specialized accelerator to verify logic tautologies [156], Perkowski proposed a general purpose accelerator for solving combinatorial problems, based on reduction of problems to generic combinatorial problems like "graph coloring" or satisfiability and implemented in a parallel systolic architecture [141].