The portion of a chip implementing a set of Boolean functions usually represents a major contribution to chip's area or system's chip count. Obviously, there are many circuits which realize the same Boolean function. Unfortunately, at present there is no general theory that provides designers (and design automation programs) with lower bounds for the total area of logic implementations in integrated systems. Therefore, the main task for computer optimization programs appear in choosing the circuit with the most convenient layout, minimizing the area but also fulfilling many other constraints like timing, power consumption, and use of standard cells. Various approaches are used for different technologies and design styles (standard cells, ROM, PLA, Weinberger layout, SLA, gate arrays, etc.).
There are many sources of non-optimality of initial specification of logic circuits. If the logic is created from FSM description, it was not minimized by the designer at all. If it is specified as a source description - it bears all non-optimalities of the way of how the designer thinks about his idea. The description of logic in integrated design automation systems is a result of hardware compilation from the high level front end system or the register-transfer language; this description is then usually non optimal and should thus be next optimized with technology independent and next technology dependent transformations based on Boolean algebra.
The logic minimization is then always a must, but different methods are applied, according to the design stage, design goals, and target technology. Therefore, two stages are incorporated in the logic optimization systems - technology independent, followed by the mapping from generic to target technology and technology-dependent optimization.
The logic circuit design methods include basically two categories: two-level and multi-level design. Two-level circuits are realized usually with Programmable Logic Arrays (PLA) or Programmable Array Logic (PAL).