This is the second term of an approved two term undergraduate and graduate sequence. The second term's goals are to continue the study of CMOS circuit and logic design. A laboratory is integrated into the lecture and students will gain skills in device and small scale integrated circuit simulation, and CMOS IC layout.

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Contact Information

Course Outcomes and Syllabus

Detailed syllabus for this course is in PDF format.

This is the second term of an approved two term undergraduate sequence and an approved three term graduate sequence. The second term’s goals are to apply the results of last term’s study of MOSFET gates and use them in small design problems; to introduce the steps used in floor-planning of digital subsystems and circuits; and introduce the study of test and manufacturability of digital MOS circuits. A laboratory is integrated into the lecture. Students will gain skills in device and small scale integrated circuit simulation and, CMOS IC layout. Graduate students are encouraged this term to complete an independent design project. The details of the project will be discussed separately.

An integral part of ABET course documentation is to define each undergraduate course using departmental program outcomes. Listed below are the outcomes for Digital Integrated Circuit Design II.

Circuits and systems

Identify and formulate problems

Design and Conduct experiments

Written communication and report writing

Understand the impact of science and technology on the economy, environment, industry and educational needs

Understand that skill training is an engineer’s responsibility

Understand that life-long learning and/or continuing education is a responsibility of every engineer

Logisitcs

Assignments

Notes

Laboratories

Other WWW URLs about IC design and CAD

A Short History Lesson

For last 15-20 years computers at universities, research institutions and many companies participated in USENET by making local and long distance phone calls to connect to a small subset of systems within USENET via modems. USENET was organized around the newsgroups that of late been confused with the Internet. Two of the oldest newsgroups were organized to discuss and exchange information about VLSI and computer aided design. One of the links is to the newsgroups for VLSI.

Textbook Support, Errata

Errata for the text is available from Addison-Wesley, the publisher, in electronic form. A valuble URL is the CMOS VLSI Design 3rd web support materials. The author provides an errata that should be checked if questions arise as well as local additions to the errata."

Dr. Rabaey, one of the authors, maintains a web-site for his textbook Digital Interated Circuits."

Links

First integrated circuit (IC) demonstrated by inventor Jack Kilby.

Silicon chips are prepared by an elaborate sequence of processing steps applied to a silicon wafer. A sample of a few

Intel provides a summary of the 90 nanometer" technology node.

IBM Research Nanotechnology IBM’s nanotechnology research aims to devise new atomic- and molecular-scale structures and devices for enhancing information technologies, as well as discover and understand their scientific foundations.

IBM Research VLSI Design Our mission is to contribute to VLSI design, microarchitecture, and performance expertise into leading-edge embedded, client, and server microprocessor designs and to explore new microarchitectures, system designs and organizations, circuits, and design tools and methodologies. A key goal is to continue to drive innovative exploratory ideas into real products.

LSI Logic largest silicon fab is located in Gresham.

Len Harold of the Microelectronics Research Center at the University of Idaho has a good collection of Web sources on VLSI topics including conference announcements etc. Some links to job opportunities and other time sensitive information are outdated.

On-line magazines are also available. Solid-State is primarily about manufacturing. A service directory for the semiconductor industry includes URLs to univeristy and industry groups.

A 1998 MOSFET device is a sub-micron architecture assembled from large number of interacting processing steps. This article in the Intel Technology Journal outlines MOSFET device architectures for the next few years and the limits of MOSFET device scaling.