This is the first term of an approved two term undergraduate sequence and an approved three term graduate sequence. The first term's goals are to learn and use in simple design problems three large signal device models for the MOSFET, to introduce the steps in MOSFET fabrication, and to begin the study of CMOS circuit and logic design. A laboratory is integrated into the lecture and students will gain skills in device and small scale integrated circuit simulation, and CMOS IC layout. Graduate students are encouraged to begin an independent design project that will be completed during the third term of the sequence.

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Syllabus

Complete Syllabus details.

This is the first term of an approved two term undergraduate sequence. The first term’s goals are to learn three large signal device models for the MOSFET and use them in simple design problems; to introduce the steps used in MOSFET fabrication and begin the study of CMOS circuit and logic design. A laboratory is integrated into the lecture. Students will gain skills in device and small scale integrated circuit simulation and, CMOS IC layout.

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Assignments

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Chapter Notes

Laboratories

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Frequently Asked Questions

Are the lectures prepared by Dr. Harris available for the textbook?

Dr. Harris notes are available from the textbook website. I added a URL under "Chapter Notes". Textbook course materials and notes are either in PDF or PPT format.

Can I work alone on the laboratory assignments?

Unfortunately, no. There are five classes using the VLSI Design Laboratory this quarter. If students worked individually there simply are not enough seats to accommodate everyone.

How big a group is allowed for the laboratory assignments?

Student teams should be limited to two or three. Teams with both undergraduate students and graduate students are allowed (encouraged).

I am taking ECE 525 from OCATE. Could you please tell me when is the first assignment due?

Chapter problems in section labeled “Homework Assignments” will not be collected. As noted in the Syllabus the grade is composed of exams and laboratories. The problems are suggested as a study guide to the chapter. As the course proceeds it possible, indeed likely, that additional problems from previous chapters may be added. Solutions to the odd problems can be found on the West and Harris textbook web page.

How should I submit laboratory work?

Laboratories will be submitted electronically as PDF file. PDF can be created from either Postscript (via ghostview) or using Adobe Standard from Word and other Windows based tools. Each laboratory assignment must declare all members of the student group.

How can I catch up on a lecture?

All lectures are streamed from the Portland State Distance Learning Center Windows Media 9 player is required.

Will there be any use of WebCT for this course?

No. WebCT is not used in either ECE 425 or ECE 525.

How do I label the inverters in lab 1?

The minimum sized inverters (diode and CMOS) are numbered 1 and 2, respectively. The longer pullups are numbered 3 and 4, respectively

How do I input a piecewise linear voltage source

The piecewise linear voltage source is named ’vpwl’ in Cadence Schematic Composer

How should we generate the compliment of In for the multiplexer input?

The easiest way is to fanout the input to a CMOS inverter. The second way is to build a second vpwl as the voltage complement to the uncomplemented (positive) input.

Mutiple inputs in NOR

Data-sheets are for single input transitions. Multiple input gates are simulated with one input making a transition and others held to a constant DC value. Worst-case simulations should set the inputs to have the active signal select the worst-case branch. This may require different setups for pullup and pulldown networks.