This is the first term of an approved two term undergraduate sequence and an approved three term graduate sequence. The first term's goals are to learn and use in simple design problems three large signal device models for the MOSFET, to introduce the steps in MOSFET fabrication, and to begin the study of CMOS circuit and logic design. A laboratory is integrated into the lecture and students will gain skills in device and small scale integrated circuit simulation, and CMOS IC layout. Graduate students are encouraged to begin an independent design project that will be completed during the third term of the sequence.

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Syllabus

Complete Syllabus details.

This is the first term of an approved two term undergraduate sequence. The first term’s goals are to learn three large signal device models for the MOSFET and use them in simple design problems; to introduce the steps used in MOSFET fabrication and begin the study of CMOS circuit and logic design. A laboratory is integrated into the lecture. Students will gain skills in device and small scale integrated circuit simulation and, CMOS IC layout.

Complete ABET Syllabus

Assignments

Announcements

Announcements are summarized.

Announcements

Chapter Notes

Laboratories

Startup

Tutorials and other information about the Cadence tools can be found at PSU ECE Cadence North American University Program.

NCSU Cadence Design Kit

The NCSU Cadence Design Kit configures the Cadence software, provides technology specific data and additional menu options. The course laboratories and the tutorials provided in the tutorial sections are designed with the NCSU CDK configuration. The startup scripts below are designed for the PSU ECE VLSI Design Laboratory. The scripts are based on a standard login (.cshrc and .login) and set all environment variables and expand the search path. At locations other than ECE at PSU modifications to pathnames in the startup scripts and the like will be required.

Startup Scripts

For NCSU CDK Version 1.3 and Cadence IC 5.1 use the C-Shell Start Up File for Cadence IC 5.1 use the Bash Start Up File for Cadence IC 5.1

Save this file to your local directory. Use the following UNIX command in the window before you run the Cadence Front to Back Integrated Circuit Design Environment command. Cadence provides several design environments. The "icfb" (IC design Front to Back) was used for all schematic entry and standard cell layouts.

% source startup.txt
% icfb &

Device Models

Copy and save in $HOME/cadence/model/spectre the Spectre device models TSMC NFET Spectre Model and the TSMC PFET Spectre Model

Tutorials about NCSU CDK

To get started the tutorials about Cadence and the NCSU CDK are useful. Sample Design Tutorial create the Cadence library (a directory structure for saving your work) and a small transistor level design. The the second is shorter. Students report difficulty with the replacing the references to Hspice in the tutorial with the Cadence Spectre used in the lab.

The Worcester Polytechnic Institute Cadence Tutorial is web based and step-by-step from specifications through post-layout simulation. The WPI alternative link doesn’t appear to be active.

Virginia Cadence Tutorials are a place to start learning the basics of schematic entry and Spectre simulation.

Bitgen

A simple perl script called bitgen helps create input stimulus for Analog Artist NCSU Bitgen. A short Bitgen Tutorial fills in a few missing steps with additional screen shots.

1. Laboratory Assignments

Laboratory assignments are listed in order.

Laboratory 1

Laboratory 2

Datasheet

Laboratory 3

Laboratory 4

All standard cells are to be a fixed, single height.

To efficiently use the physical layouts the standard cells must meet a specific grid spacing, cell height as well contact and via placement.

See Layout setup and Virtuoso Tutorial.

Remember the same height has to be used for all standard cells and the contacts must land on the 10x10 grid to use the router.

2. Lab Grading Outline

You will receive a list of numbers via email to the lab partner that submitted the laboratory assignment. The scoring is described in order from left to right.

2.1. Laboratory Grade Review

Laboratory 1

This laboratory is primary to familiarize students with the Cadence tool set and the basic operations of schematic entry, Spectre simulation, and the use of the Waveform Calculator for post-simulation analysis.

The key observation from the simulation of the circuitry is

Diode connected inverters have diminished output swing, gain, transient response compared to comparably sized static CMOS.

Use EPS not bitmaps. File format is PDF. Subject line "ECE x25 Group X Lab Y"

P1 (10 points) - All seven schematics and simulation results

P2 (6 points) - Table (Readings)

P3 (4 points) - Answers to the questions

In Section P1, 1 error results in reduction of 3 points, 2 errors results in reduction of 5 points. More than 2 errors results in 0 pts. Example of an errors is a missing I/O pin, PWL, capacitor, Power Supply, schematic, DC or transient response. All transistors should be sized according to the specification for all seven schematics.

In Section P2, 1 error in the table results in reduction of 1 point. The table should reflect the change in the length or width of the transistors and should include readings for CMOS 1, CMOS 2, Diode 1 and Diode 2.

In Section P3, each question was worth 2 points. The answer should indicate why you got a variation in the table by changing the length or width of the transistors and the type of inverter.

2.2. Laboratory 2 and Laboratory 3

P1 (5 points) - Inverter Cell description

P2 (15 points) - AOI cell description

P3 (20 points) - Performance analysis of Inverter

P4 (60 points) - Performance analysis of AOI

In Section P1, each of Cell Description, Cell Symbol, Cell Truth Table, Cell Schematic diagram and Cell dimensions is worth 1 point. Points were deducted for following kinds of errors: Schematic is not in publication format, I/O pin is not bidirectional, truth table is incorrect, incorrect symbol etc.

In Section P2, each of Cell Description, Cell Symbol, Cell Truth Table, Cell Schematic diagram and Cell dimensions is worth 3 points. Points were deducted for following kinds of errors: Schematic is not in publication format, I/O pin is not bidirectional, truth table is incorrect, incorrect symbol etc.

In Section P3, Rise and Fall Time table is worth 8 points. TPLH and TPHL table is worth 7 points. Propagation Delay table is worth 5 points. The tables should reflect the effect of Input Slew rate increase and Output load change. Points were deducted for missing data.

In Section P4, Rise and Fall Time tables are worth 24 points. TPLH and TPHL tables are worth 21 points. Propagation Delay tables are worth 15 points. The tables should reflect the effect of Input Slew rate increase and Output load change. Points were deducted for missing data.

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