Homework2 is the synthesis and analysis part of Homework1. Refer to Homework1 for a description of the “Total Sum” operation. Shown in this homework is

the synthesis results of each of the three modules in the “Total Sum” design.

The Results of the synthesis for the “Total Sum” design are shown below. Multiple synthesis runs were completed varying from optimizing for Area, optimizing for

delay, and using the provided Auto optimization. Synthesis runs were also completed that consisted of 1, 2, 3, and 4 passes. Each of the synthesis optimizations

provided much of the same results. The only difference seemed to be in the amount of LC’s used. I believe the reason that many of the synthesis runs provided

the same results is because the design is rather small and simple – thus not requiring much effort to synthesize. The part chosen for the synthesis is an Altera part

with part + EPF10K10QC208. The synthesis properties were attained by running Exemplar’s Leonardo Spectrum, but due to license expirations the actual

shcematics shown below were synthesized in Synplicity’s synplify_pro. Table 1 shows a list of results acquired during the synthesis runs.

Property	Usage
LC’s	33
Delay	11
DFF’s	26
TRI’s	0
PI’s	21
PO’s	26
CASCADES	2
Memory Bits	0
CARRYS	0

Table 1. Listing of synthesis output usage.

The first module is the ‘counter’ circuitry. The counter is 8 bits and starts at zero and counts up until a reset is asserted. This is done by implemening a full adder that

adds one to the count on each clock cycle. To think about an adder in hardware terms it is easiest to look at what the bit patterns would look like: Lets just look at

the first 10 clock cycles:

0000 bit0 à toggles on every clock cycle.

0001 bit1 à bit1 xor bit0

0010 bit2 à bit2 xor (bit0 and bit1)

0011 bit3 à bit3 xor (bit0 and bit1 and bit2)

0100 …

0101 …

0110 bit8 à bit8 xor (bit0 and bit1 and bit2 and bit3 and bit4 and bit5 and bit6 and bit7)

0111

1000

As shown in Figure 1, the RTL schematic for the Counter matches exactly what is expected from hardware synthesis.

The second module is the ‘equivalence tester’ circuitry. It compares the inputs which are both 8 bits: ‘input_count’ and ‘input_number’ and decides whether the

counter has counted up to the chosen input number. This is done by comparing each bit of the count and number and testing them for equality. In hardware this is

done by xor’ing each bit and and’ing the output of all of the xor gates together. If the output is ‘0’ then all bits were equal. This RTL schematic is shown in Figure 2.

The technology schematic is also shown for this module in Figure 2. The technology schematic is the RTL schematic mapped into the technology that is actually used

when an FPGA is created. As can be seen, the technology schematic is not easy to understand.

The last module is the ‘summation’ circuitry. It basically starts at a count of zero, and adds the numbers from 1 to a predetermined final_count. For example: if

final_count = 5, then final_output = 1+2+3+4+5 = 15. This is done by having one variable ‘temp_add’ that contains the amount to be added to the final_output at

each clock cycle. The temp_add variable starts at 0, then goes to 1,2,3,4…final_count. Thus, on each clock cycle, the temp_add variable is added to the

final_output as shown above. The temp_add variable in hardware is nothing new because it is incremented by one on each clock cycle in the same manner as the

‘counter’ circuitry. The final_output is implemented in hardware as a simple adder that continually adds the current final_output value to the temp_add variable on

each clock cycle. This can be seen below in Figure 4.

Figure 3. Equivalence technology schematic