Homework1: Running Sum
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Overview:
The running sum machine allows the user to input any 8-bit number and the machine will count up to that number while tallying a running sum.
Detailed Description:
The VHDL description was done using a tool called FPGA-Advantage from mentor and is available at http://www.mentor.com/fpga-advantage/. You can get a free evaluation copy of modelsim, HDL Designer, and Leonardo Spectrum for your PC.
The tutorial under the help section was very helpful. It showed how to design code using vhdl, block and wiring diagrams, flow charts, state and truth tables, and more. It also guided me through the design and simulation tools (Renior) and the synthesis tools (Leonardo). The tutorial does take about 6 hours.
The design for the Running Sum circuit was broken into three blocks: the counter, summer, and equivalence tester. The counter starts at zero and counts up until it gets a reset. The summer calculates the running sum by first starting at zero and adding one, then two, then three, etc. For example, if the input number was four then the summer would add 1+2+3+4 = 10. The summing circuitry will start back at zero upon a reset. The eqivalence tester checks to see whether the count is equal to the input number. If they are not equal then the count will continue. If they are equal then the input number has been reached and a done signal and clear signal are generated.
Process:
The running sum design was completed using block diagrams, vhdl code, and flow charts. The design was basically done in four steps. First, design the counter and test circuitry for the counter. Second, design and simulate the summer and summer test circuitry. Then, design and simulate the equivalence and equivalence test circuitry. Lastly, put all three blocks together and simulate the complete design.
Designing the counter was done by opening a block diagram schematic through the console window. Then using the schematic drawing tools a block was placed on the schematic. Two inputs were added to the block: clock and clear. One output was added to the block: output_count(7 downto 0) ŕ 8 bits. Then by double-clicking on the block, naming the block, and choosing to open a vhdl file in the selection window the coding for the block could be done. The code is shown in the presentation. Drawing the schematic with input and output ports creates the code necessary for controlling inputs/outputs so they don’t have to be entered into the vhdl code (they automatically are). Once the design of the counter was done and simulated I added test circuitry so that I could see that the counter actually worked. While in the schematic view I created a test block by going to FileŕNewŕCreate Test Bench. The created test bench contains the input signal: output_count(7 downto 0) and the ouput signals: clock, clear. The reason for the test bench is that at simulation time, waveforms for clear and clock can be generated and the signal output_count can be monitored. I implemented this using the flow chart tool and adding state changes and wait statements. To actually see the signals in a waveform the design must first be saved, compiled, linked, and simulated. Then by clicking on the signals in the diagram they can be added to the wave tool and viewed.
Designing the equivalence and summation circuitry was done in the same manner as the counter. The only difference in the designs is the actual design of the vhdl code. The equivalence design had three inputs: clock, output_count, and input_number. The design had two outputs: done and clear. The summation design had two inputs: clock, clear and it had one output: output_sum.
After all three individual block parts of the design were complete a new schematic view was created. By using the ‘place component’ option in the toolbox and selecting the correct library and parts I added a counter, equivalence tester, and summation block to the schematic. I then connected the signals as needed and shown in the presentation. Then by saving and compiling and linking all of the necessary port connection code was generated. The next step was to add a test bench and simulate. The ouput waveforms are also shown in the presentation.
Conclusion:
The FPGA-Advantage tools are very powerful, but also tedious to learn. Designing the code to run the design was not hard conceptually, but there are many syntacticle, logical and other rules that must be learned and followed.
The design compiled and simulated correctly as expected (hoped). The next step after simulation is to see if the design is actually synthesizable and what optimizations are possible. That is reserved for Homework2.