-- sorter_tb.vhd (ECE510 VHDL project-1) -- testbench for testing sorter -- Mani Suhda Yalamanchi (prasad@ece.pdx.edu) -- 4/18/2001 entity sorter_tb is end sorter_tb; architecture tb_arch of sorter_tb is type test_vector is record clk: bit; rst: bit; vld: bit; data: bit_vector (15 downto 0); sdat: bit_vector (63 downto 0); end record; type test_vector_array is array (natural range <>) of test_vector; constant test_vectors : test_vector_array := ( -- reset the sorter (clk => '1', rst => '1', vld => '0', data => x"0000", sdat => x"0000000000000000"), (clk => '0', rst => '1', vld => '0', data => x"0000", sdat => x"0000000000000000"), -- apply inputs to the sorter (clk => '1', rst => '0', vld => '1', data => x"605d", sdat => x"0000000000000000"), (clk => '0', rst => '0', vld => '1', data => x"605d", sdat => x"0000000000000000"), (clk => '1', rst => '0', vld => '1', data => x"cc0b", sdat => x"605d000000000000"), (clk => '0', rst => '0', vld => '1', data => x"cc0b", sdat => x"605d000000000000"), (clk => '1', rst => '0', vld => '1', data => x"6def", sdat => x"cc0b605d00000000"), (clk => '0', rst => '0', vld => '1', data => x"6def", sdat => x"cc0b605d00000000"), (clk => '1', rst => '0', vld => '1', data => x"cb8f", sdat => x"cc0b6def605d0000"), (clk => '0', rst => '0', vld => '1', data => x"cb8f", sdat => x"cc0b6def605d0000"), (clk => '1', rst => '0', vld => '1', data => x"7239", sdat => x"cc0bcb8f6def605d"), (clk => '0', rst => '0', vld => '1', data => x"7239", sdat => x"cc0bcb8f6def605d"), (clk => '1', rst => '0', vld => '1', data => x"27c3", sdat => x"cc0bcb8f72396def"), (clk => '0', rst => '0', vld => '1', data => x"27c3", sdat => x"cc0bcb8f72396def"), (clk => '1', rst => '0', vld => '1', data => x"8fb9", sdat => x"cb8f72396def27c3"), (clk => '0', rst => '0', vld => '1', data => x"8fb9", sdat => x"cb8f72396def27c3"), (clk => '1', rst => '0', vld => '1', data => x"68af", sdat => x"cb8f8fb9723927c3"), (clk => '0', rst => '0', vld => '1', data => x"68af", sdat => x"cb8f8fb9723927c3"), (clk => '1', rst => '0', vld => '1', data => x"1bdb", sdat => x"8fb9723968af27c3"), (clk => '0', rst => '0', vld => '1', data => x"1bdb", sdat => x"8fb9723968af27c3"), (clk => '1', rst => '0', vld => '1', data => x"7129", sdat => x"8fb968af27c31bdb"), (clk => '0', rst => '0', vld => '1', data => x"7129", sdat => x"8fb968af27c31bdb"), (clk => '1', rst => '0', vld => '1', data => x"a3c9", sdat => x"8fb9712968af1bdb"), (clk => '0', rst => '0', vld => '1', data => x"a3c9", sdat => x"8fb9712968af1bdb"), (clk => '1', rst => '0', vld => '1', data => x"7cbf", sdat => x"a3c9712968af1bdb"), (clk => '0', rst => '0', vld => '1', data => x"7cbf", sdat => x"a3c9712968af1bdb"), (clk => '1', rst => '0', vld => '1', data => x"9807", sdat => x"a3c97cbf71291bdb"), (clk => '0', rst => '0', vld => '1', data => x"9807", sdat => x"a3c97cbf71291bdb"), (clk => '1', rst => '0', vld => '1', data => x"008f", sdat => x"a3c998077cbf7129"), (clk => '0', rst => '0', vld => '1', data => x"008f", sdat => x"a3c998077cbf7129"), (clk => '1', rst => '0', vld => '1', data => x"a7f1", sdat => x"a3c998077cbf008f"), (clk => '0', rst => '0', vld => '1', data => x"a7f1", sdat => x"a3c998077cbf008f"), (clk => '1', rst => '0', vld => '1', data => x"f86f", sdat => x"a7f198077cbf008f"), (clk => '0', rst => '0', vld => '1', data => x"f86f", sdat => x"a7f198077cbf008f"), (clk => '1', rst => '0', vld => '1', data => x"71d5", sdat => x"f86fa7f19807008f"), (clk => '0', rst => '0', vld => '1', data => x"71d5", sdat => x"f86fa7f19807008f"), (clk => '1', rst => '0', vld => '1', data => x"5f67", sdat => x"f86fa7f171d5008f"), (clk => '0', rst => '0', vld => '1', data => x"5f67", sdat => x"f86fa7f171d5008f"), (clk => '1', rst => '0', vld => '1', data => x"f3f3", sdat => x"f86fa7f171d55f67"), (clk => '0', rst => '0', vld => '1', data => x"f3f3", sdat => x"f86fa7f171d55f67"), (clk => '1', rst => '0', vld => '1', data => x"83cf", sdat => x"f86ff3f371d55f67"), (clk => '0', rst => '0', vld => '1', data => x"83cf", sdat => x"f86ff3f371d55f67"), (clk => '1', rst => '0', vld => '1', data => x"fddb", sdat => x"f3f383cf71d55f67"), (clk => '0', rst => '0', vld => '1', data => x"fddb", sdat => x"f3f383cf71d55f67"), (clk => '1', rst => '0', vld => '1', data => x"f525", sdat => x"fddbf3f383cf5f67"), (clk => '0', rst => '0', vld => '1', data => x"f525", sdat => x"fddbf3f383cf5f67"), (clk => '1', rst => '0', vld => '1', data => x"a18b", sdat => x"fddbf525f3f383cf"), (clk => '0', rst => '0', vld => '1', data => x"a18b", sdat => x"fddbf525f3f383cf"), (clk => '1', rst => '0', vld => '1', data => x"52eb", sdat => x"fddbf525a18b83cf"), (clk => '0', rst => '0', vld => '1', data => x"52eb", sdat => x"fddbf525a18b83cf"), (clk => '1', rst => '0', vld => '1', data => x"2eeb", sdat => x"fddbf525a18b52eb"), (clk => '0', rst => '0', vld => '1', data => x"2eeb", sdat => x"fddbf525a18b52eb"), (clk => '1', rst => '0', vld => '1', data => x"a993", sdat => x"f525a18b52eb2eeb"), (clk => '0', rst => '0', vld => '1', data => x"a993", sdat => x"f525a18b52eb2eeb"), (clk => '1', rst => '0', vld => '1', data => x"7bd1", sdat => x"a993a18b52eb2eeb"), (clk => '0', rst => '0', vld => '1', data => x"7bd1", sdat => x"a993a18b52eb2eeb"), (clk => '1', rst => '0', vld => '1', data => x"abdf", sdat => x"a9937bd152eb2eeb"), (clk => '0', rst => '0', vld => '1', data => x"abdf", sdat => x"a9937bd152eb2eeb"), (clk => '1', rst => '0', vld => '1', data => x"fe49", sdat => x"abdfa9937bd12eeb"), (clk => '0', rst => '0', vld => '1', data => x"fe49", sdat => x"abdfa9937bd12eeb"), (clk => '1', rst => '0', vld => '1', data => x"54a5", sdat => x"fe49abdfa9937bd1"), (clk => '0', rst => '0', vld => '1', data => x"54a5", sdat => x"fe49abdfa9937bd1"), (clk => '1', rst => '0', vld => '1', data => x"6e45", sdat => x"fe49abdf7bd154a5"), (clk => '0', rst => '0', vld => '1', data => x"6e45", sdat => x"fe49abdf7bd154a5"), (clk => '1', rst => '0', vld => '1', data => x"b66f", sdat => x"fe49abdf6e4554a5"), (clk => '0', rst => '0', vld => '1', data => x"b66f", sdat => x"fe49abdf6e4554a5"), (clk => '1', rst => '0', vld => '1', data => x"1f6b", sdat => x"fe49b66f6e4554a5"), (clk => '0', rst => '0', vld => '1', data => x"1f6b", sdat => x"fe49b66f6e4554a5"), (clk => '1', rst => '0', vld => '1', data => x"53d7", sdat => x"b66f6e4554a51f6b"), (clk => '0', rst => '0', vld => '1', data => x"53d7", sdat => x"b66f6e4554a51f6b"), (clk => '1', rst => '0', vld => '1', data => x"eb3b", sdat => x"b66f6e4553d71f6b"), (clk => '0', rst => '0', vld => '1', data => x"eb3b", sdat => x"b66f6e4553d71f6b"), (clk => '1', rst => '0', vld => '1', data => x"ad23", sdat => x"eb3bb66f53d71f6b"), (clk => '0', rst => '0', vld => '1', data => x"ad23", sdat => x"eb3bb66f53d71f6b"), (clk => '1', rst => '0', vld => '1', data => x"3725", sdat => x"eb3bad2353d71f6b"), (clk => '0', rst => '0', vld => '1', data => x"3725", sdat => x"eb3bad2353d71f6b"), (clk => '1', rst => '0', vld => '1', data => x"1d01", sdat => x"eb3bad2353d73725"), (clk => '0', rst => '0', vld => '1', data => x"1d01", sdat => x"eb3bad2353d73725"), (clk => '1', rst => '0', vld => '1', data => x"41d7", sdat => x"eb3bad2337251d01"), (clk => '0', rst => '0', vld => '1', data => x"41d7", sdat => x"eb3bad2337251d01"), (clk => '1', rst => '0', vld => '1', data => x"07dd", sdat => x"ad2341d737251d01"), (clk => '0', rst => '0', vld => '1', data => x"07dd", sdat => x"ad2341d737251d01"), (clk => '1', rst => '0', vld => '1', data => x"4e65", sdat => x"41d737251d0107dd"), (clk => '0', rst => '0', vld => '1', data => x"4e65", sdat => x"41d737251d0107dd"), (clk => '1', rst => '0', vld => '1', data => x"26b3", sdat => x"4e6541d71d0107dd"), (clk => '0', rst => '0', vld => '1', data => x"26b3", sdat => x"4e6541d71d0107dd"), (clk => '1', rst => '0', vld => '1', data => x"5b83", sdat => x"4e6541d726b307dd"), (clk => '0', rst => '0', vld => '1', data => x"5b83", sdat => x"4e6541d726b307dd"), (clk => '1', rst => '0', vld => '1', data => x"b7ed", sdat => x"5b834e6526b307dd"), (clk => '0', rst => '0', vld => '1', data => x"b7ed", sdat => x"5b834e6526b307dd"), (clk => '1', rst => '0', vld => '1', data => x"b873", sdat => x"b7ed5b834e6526b3"), (clk => '0', rst => '0', vld => '1', data => x"b873", sdat => x"b7ed5b834e6526b3"), (clk => '1', rst => '0', vld => '1', data => x"fe09", sdat => x"b873b7ed5b8326b3"), (clk => '0', rst => '0', vld => '1', data => x"fe09", sdat => x"b873b7ed5b8326b3"), (clk => '1', rst => '0', vld => '1', data => x"d8eb", sdat => x"fe09b873b7ed5b83"), (clk => '0', rst => '0', vld => '1', data => x"d8eb", sdat => x"fe09b873b7ed5b83"), (clk => '1', rst => '0', vld => '1', data => x"0daf", sdat => x"fe09d8ebb873b7ed"), (clk => '0', rst => '0', vld => '1', data => x"0daf", sdat => x"fe09d8ebb873b7ed"), (clk => '1', rst => '0', vld => '1', data => x"249b", sdat => x"fe09d8ebb8730daf"), (clk => '0', rst => '0', vld => '1', data => x"249b", sdat => x"fe09d8ebb8730daf"), (clk => '1', rst => '0', vld => '1', data => x"e201", sdat => x"fe09d8eb249b0daf"), (clk => '0', rst => '0', vld => '1', data => x"e201", sdat => x"fe09d8eb249b0daf"), (clk => '1', rst => '0', vld => '1', data => x"0673", sdat => x"e201d8eb249b0daf"), (clk => '0', rst => '0', vld => '1', data => x"0673", sdat => x"e201d8eb249b0daf"), (clk => '1', rst => '0', vld => '1', data => x"5fa1", sdat => x"e201249b0daf0673"), (clk => '0', rst => '0', vld => '1', data => x"5fa1", sdat => x"e201249b0daf0673"), (clk => '1', rst => '0', vld => '1', data => x"1373", sdat => x"e2015fa1249b0673"), (clk => '0', rst => '0', vld => '1', data => x"1373", sdat => x"e2015fa1249b0673"), (clk => '1', rst => '0', vld => '1', data => x"bc5d", sdat => x"e2015fa113730673"), (clk => '0', rst => '0', vld => '1', data => x"bc5d", sdat => x"e2015fa113730673"), (clk => '1', rst => '0', vld => '1', data => x"a02b", sdat => x"bc5d5fa113730673"), (clk => '0', rst => '0', vld => '1', data => x"a02b", sdat => x"bc5d5fa113730673"), (clk => '1', rst => '0', vld => '1', data => x"0af9", sdat => x"bc5da02b5fa11373"), (clk => '0', rst => '0', vld => '1', data => x"0af9", sdat => x"bc5da02b5fa11373"), (clk => '1', rst => '0', vld => '1', data => x"6789", sdat => x"bc5da02b13730af9") ); signal clock : bit; signal reset : bit; signal valid : bit; signal data : bit_vector(15 downto 0); signal sorted_data : bit_vector(63 downto 0); component sorter generic (w : integer := 8; n : integer := 8); port (clock : in bit; reset : in bit; valid : in bit; data : in bit_vector(w-1 downto 0); sorted_data: out bit_vector((n*w)-1 downto 0)); end component; begin -- instantiate a 4 entry 16 bit sorter. uut: sorter generic map ( w => 16, n => 4 ) port map ( clock => clock, reset => reset, valid => valid, data => data, sorted_data => sorted_data ); verify: process variable vector : test_vector; variable errors : boolean := false; begin -- apply test vectors and check results. for i in test_vectors'range loop -- get vector i vector := test_vectors(i); -- schedule vector i clock <= vector.clk; reset <= vector.rst; valid <= vector.vld; data <= vector.data; -- wait for circuit to settle wait for 20 ns; -- check output vectors if sorted_data /= vector.sdat then assert false report "sorter produced wrong value" severity error; errors := true; end if; end loop; assert not errors report "Test Vectors failed." severity note; assert errors report "Test Vectors passed." severity note; wait; end process; end tb_arch;