**************************************** Report : timing -path full -delay max -max_paths 20 -transition_time Design : fpu Version: 2000.11-SP1 Date : Sun Jul 8 17:11:22 2001 **************************************** Operating Conditions: WCCOM Library: 1m0_typ Wire Load Model Mode: top Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg2[31] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U3157/o (1m0ca03x20) 0.11 0.10 7.87 f u4/U3277/o (1m0na04x50) 0.07 0.08 7.95 r u4/U2981/o (1m0in00x30) 0.05 0.04 8.00 f u4/U2530/o (1m0mx22x20) 0.03 0.07 8.07 f u4/U3156/o (1m0an02x05) 0.06 0.08 8.16 f u4/U2850/o (1m0or03x20) 0.03 0.08 8.24 f u4/U2847/o (1m0an03x20) 0.03 0.07 8.31 f u4/U3279/o (1m0or03x40) 0.05 0.08 8.40 f u4/U2958/o (1m0in00x50) 0.05 0.05 8.45 r u4/U3054/o (1m0na02x20) 0.06 0.05 8.50 f u4/U2939/o (1m0in00x20) 0.04 0.04 8.54 r u4/U2938/o (1m0na02x20) 0.08 0.06 8.60 f u4/U3234/o (1m0co01x50) 0.09 0.08 8.68 r u4/U2948/o (1m0na02x30) 0.06 0.04 8.72 f u4/U3272/o (1m0na03x50) 0.08 0.07 8.79 r u4/U3053/o (1m0bf00x60) 0.10 0.10 8.89 r u4/U2985/o (1m0no02x20) 0.09 0.06 8.95 f U770/o (1m0or03x10) 0.05 0.12 9.06 f U1853/o (1m0or03x20) 0.03 0.08 9.14 f U1854/o (1m0or03x20) 0.03 0.07 9.21 f U1836/o (1m0or03x20) 0.07 0.11 9.32 f U923/o (1m0in00x50) 0.03 0.03 9.35 r U1839/o (1m0na02x30) 0.06 0.05 9.41 f U1079/o (1m0in00x30) 0.07 0.07 9.47 r U1858/o (1m0na02x30) 0.07 0.05 9.53 f U1859/o (1m0in01x70) 0.03 0.03 9.56 r U1845/o (1m0mx22x20) 0.03 0.07 9.63 f U1846/o (1m0mx22x20) 0.03 0.07 9.71 f U1847/o (1m0mx22x20) 0.03 0.07 9.78 f U1317/o (1m0mx22x10) 0.05 0.08 9.86 f U1848/o (1m0mx22x20) 0.03 0.07 9.94 f fpout_reg2[31]/d (1m0ma04x10) 0.03 0.00 9.94 f data arrival time 9.94 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg2[31]/ck (1m0ma04x10) 0.00 10.00 r library setup time -0.06 9.94 data required time 9.94 -------------------------------------------------------------------------- data required time 9.94 data arrival time -9.94 -------------------------------------------------------------------------- slack (MET) 0.01 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: zero_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U3157/o (1m0ca03x20) 0.11 0.10 7.87 f u4/U3277/o (1m0na04x50) 0.07 0.08 7.95 r u4/U2981/o (1m0in00x30) 0.05 0.04 8.00 f u4/U2530/o (1m0mx22x20) 0.03 0.07 8.07 f u4/U3156/o (1m0an02x05) 0.06 0.08 8.16 f u4/U2850/o (1m0or03x20) 0.03 0.08 8.24 f u4/U2847/o (1m0an03x20) 0.03 0.07 8.31 f u4/U3279/o (1m0or03x40) 0.05 0.08 8.40 f u4/U2958/o (1m0in00x50) 0.05 0.05 8.45 r u4/U3054/o (1m0na02x20) 0.06 0.05 8.50 f u4/U2939/o (1m0in00x20) 0.04 0.04 8.54 r u4/U2938/o (1m0na02x20) 0.08 0.06 8.60 f u4/U3234/o (1m0co01x50) 0.09 0.08 8.68 r u4/U2948/o (1m0na02x30) 0.06 0.04 8.72 f u4/U3272/o (1m0na03x50) 0.08 0.07 8.79 r u4/U3053/o (1m0bf00x60) 0.10 0.10 8.89 r u4/U2985/o (1m0no02x20) 0.09 0.06 8.95 f U770/o (1m0or03x10) 0.05 0.12 9.06 f U1853/o (1m0or03x20) 0.03 0.08 9.14 f U1854/o (1m0or03x20) 0.03 0.07 9.21 f U1836/o (1m0or03x20) 0.07 0.11 9.32 f U923/o (1m0in00x50) 0.03 0.03 9.35 r U1839/o (1m0na02x30) 0.06 0.05 9.41 f U911/o (1m0na02x20) 0.06 0.05 9.46 r U1074/o (1m0na03x10) 0.12 0.09 9.55 f U1072/o (1m0mx22x10) 0.04 0.10 9.65 f U1323/o (1m0mx22x10) 0.04 0.08 9.74 f U1319/o (1m0co01x10) 0.17 0.13 9.87 r zero_reg/d (1m0ma04x05) 0.17 0.00 9.87 r data arrival time 9.87 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 zero_reg/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.09 9.91 data required time 9.91 -------------------------------------------------------------------------- data required time 9.91 data arrival time -9.87 -------------------------------------------------------------------------- slack (MET) 0.04 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: ine_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2987/o (1m0co01x10) 0.22 0.18 9.07 r U1370/o (1m0in00x20) 0.09 0.08 9.14 f U1855/o (1m0na04x30) 0.07 0.08 9.22 r U1837/o (1m0or03x20) 0.06 0.08 9.30 r U922/o (1m0in00x20) 0.03 0.03 9.34 f U1839/o (1m0na02x30) 0.07 0.06 9.40 r U1079/o (1m0in00x30) 0.05 0.05 9.45 f U1858/o (1m0na02x30) 0.08 0.06 9.51 r U1859/o (1m0in01x70) 0.03 0.04 9.55 f U1104/o (1m0ko01x15) 0.16 0.11 9.66 r U1422/o (1m0or03x10) 0.05 0.08 9.74 r U1418/o (1m0na03x10) 0.13 0.09 9.83 f ine_reg/d (1m0ma04x05) 0.13 0.00 9.83 f data arrival time 9.83 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 ine_reg/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.10 9.90 data required time 9.90 -------------------------------------------------------------------------- data required time 9.90 data arrival time -9.83 -------------------------------------------------------------------------- slack (MET) 0.06 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: underflow_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2987/o (1m0co01x10) 0.22 0.18 9.07 r U1370/o (1m0in00x20) 0.09 0.08 9.14 f U1855/o (1m0na04x30) 0.07 0.08 9.22 r U1837/o (1m0or03x20) 0.06 0.08 9.30 r U921/o (1m0na02x20) 0.04 0.04 9.34 f U1078/o (1m0ca07x10) 0.23 0.20 9.54 r U1077/o (1m0na02x10) 0.11 0.09 9.63 f U1335/o (1m0na03x10) 0.14 0.13 9.76 r U1334/o (1m0na02x10) 0.09 0.09 9.85 f underflow_reg/d (1m0ma04x05) 0.09 0.00 9.85 f data arrival time 9.85 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 underflow_reg/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.09 9.91 data required time 9.91 -------------------------------------------------------------------------- data required time 9.91 data arrival time -9.85 -------------------------------------------------------------------------- slack (MET) 0.06 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: inf_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2982/o (1m0co01x10) 0.22 0.18 9.07 r U1357/o (1m0in00x20) 0.09 0.07 9.14 f U926/o (1m0or03x10) 0.04 0.12 9.26 f U925/o (1m0or03x10) 0.04 0.09 9.35 f U1086/o (1m0or03x10) 0.04 0.10 9.45 f U1080/o (1m0co07x10) 0.24 0.18 9.63 r U1346/o (1m0na02x10) 0.11 0.10 9.73 f U1345/o (1m0na02x10) 0.12 0.10 9.83 r inf_reg/d (1m0ma04x05) 0.12 0.00 9.83 r data arrival time 9.83 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 inf_reg/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.83 -------------------------------------------------------------------------- slack (MET) 0.09 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: overflow_reg (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U3157/o (1m0ca03x20) 0.11 0.10 7.87 f u4/U3277/o (1m0na04x50) 0.07 0.08 7.95 r u4/U2981/o (1m0in00x30) 0.05 0.04 8.00 f u4/U2530/o (1m0mx22x20) 0.03 0.07 8.07 f u4/U3156/o (1m0an02x05) 0.06 0.08 8.16 f u4/U2850/o (1m0or03x20) 0.03 0.08 8.24 f u4/U2847/o (1m0an03x20) 0.03 0.07 8.31 f u4/U3279/o (1m0or03x40) 0.05 0.08 8.40 f u4/U2958/o (1m0in00x50) 0.05 0.05 8.45 r u4/U3054/o (1m0na02x20) 0.06 0.05 8.50 f u4/U2939/o (1m0in00x20) 0.04 0.04 8.54 r u4/U2938/o (1m0na02x20) 0.08 0.06 8.60 f u4/U3234/o (1m0co01x50) 0.09 0.08 8.68 r u4/U2927/o (1m0in00x10) 0.06 0.06 8.74 f u4/U2926/o (1m0co03x10) 0.21 0.14 8.87 r u4/U2995/o (1m0mx22x05) 0.18 0.19 9.06 r U1393/o (1m0in00x10) 0.08 0.07 9.13 f U1389/o (1m0ko01x10) 0.22 0.18 9.30 r overflow_reg/d (1m0ma04x05) 0.22 0.00 9.30 r data arrival time 9.30 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 overflow_reg/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.10 9.90 data required time 9.90 -------------------------------------------------------------------------- data required time 9.90 data arrival time -9.30 -------------------------------------------------------------------------- slack (MET) 0.60 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[27] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U3000/o (1m0co01x10) 0.22 0.18 9.07 r U1417/o (1m0in00x20) 0.09 0.07 9.14 f U1416/o (1m0na02x05) 0.19 0.16 9.30 r fpout_reg[27]/d (1m0ma04x05) 0.19 0.00 9.30 r data arrival time 9.30 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[27]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.09 9.91 data required time 9.91 -------------------------------------------------------------------------- data required time 9.91 data arrival time -9.30 -------------------------------------------------------------------------- slack (MET) 0.61 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[28] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2992/o (1m0co01x10) 0.22 0.18 9.07 r U1386/o (1m0in00x20) 0.08 0.07 9.14 f U1385/o (1m0na02x05) 0.19 0.16 9.30 r fpout_reg[28]/d (1m0ma04x05) 0.19 0.00 9.30 r data arrival time 9.30 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[28]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.09 9.91 data required time 9.91 -------------------------------------------------------------------------- data required time 9.91 data arrival time -9.30 -------------------------------------------------------------------------- slack (MET) 0.61 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[24] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2987/o (1m0co01x10) 0.22 0.18 9.07 r U1370/o (1m0in00x20) 0.09 0.08 9.14 f U1369/o (1m0na02x10) 0.11 0.10 9.24 r fpout_reg[24]/d (1m0ma04x05) 0.11 0.00 9.24 r data arrival time 9.24 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[24]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.24 -------------------------------------------------------------------------- slack (MET) 0.68 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[29] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2982/o (1m0co01x10) 0.22 0.18 9.07 r U1357/o (1m0in00x20) 0.09 0.07 9.14 f U1356/o (1m0na02x10) 0.13 0.10 9.24 r fpout_reg[29]/d (1m0ma04x05) 0.13 0.00 9.24 r data arrival time 9.24 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[29]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.24 -------------------------------------------------------------------------- slack (MET) 0.68 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[30] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2980/o (1m0co01x10) 0.22 0.18 9.07 r U1355/o (1m0in00x20) 0.09 0.07 9.14 f U1354/o (1m0na02x10) 0.11 0.10 9.24 r fpout_reg[30]/d (1m0ma04x05) 0.11 0.00 9.24 r data arrival time 9.24 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[30]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.24 -------------------------------------------------------------------------- slack (MET) 0.68 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[26] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2974/o (1m0co01x10) 0.22 0.18 9.07 r U1331/o (1m0in00x20) 0.09 0.07 9.14 f U1330/o (1m0na02x10) 0.11 0.10 9.24 r fpout_reg[26]/d (1m0ma04x05) 0.11 0.00 9.24 r data arrival time 9.24 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[26]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.24 -------------------------------------------------------------------------- slack (MET) 0.68 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[25] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2806/o (1m0na04x10) 0.27 0.26 7.66 r u4/U2965/o (1m0in00x50) 0.10 0.08 7.74 f u4/U2881/o (1m0ca03x05) 0.34 0.26 8.00 r u4/U2879/o (1m0na04x20) 0.14 0.11 8.11 f u4/U2342/o (1m0na04x20) 0.09 0.10 8.21 r u4/U3173/o (1m0or03x20) 0.11 0.12 8.33 r u4/U3264/o (1m0or03x20) 0.04 0.07 8.40 r u4/U2786/o (1m0na02x20) 0.07 0.04 8.43 f u4/U2782/o (1m0na03x15) 0.13 0.11 8.54 r u4/U3238/o (1m0na02x30) 0.07 0.06 8.61 f u4/U2959/o (1m0co01x10) 0.21 0.16 8.77 r u4/U2594/o (1m0in00x20) 0.13 0.12 8.89 f u4/U2989/o (1m0co01x10) 0.22 0.18 9.07 r U1374/o (1m0in00x20) 0.08 0.07 9.14 f U1373/o (1m0na02x10) 0.11 0.10 9.24 r fpout_reg[25]/d (1m0ma04x05) 0.11 0.00 9.24 r data arrival time 9.24 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[25]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.24 -------------------------------------------------------------------------- slack (MET) 0.68 Startpoint: fpu_op_r2_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fract_i2f_reg[47] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path ----------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r2_reg[2]/ck (1m0ma04x05) 0.00 0.00 0.00 r fpu_op_r2_reg[2]/o (1m0ma04x05) 0.20 0.18 0.18 r U1125/o (1m0in00x10) 0.19 0.18 0.35 f U1126/o (1m0or03x10) 0.12 0.20 0.55 f U1314/o (1m0bf00x60) 0.06 0.10 0.65 f U1535/o (1m0in00x110) 0.13 0.11 0.76 r U1063/o (1m0na02x10) 0.09 0.08 0.84 f r107/U54/o (1m0in00x10) 0.16 0.14 0.98 r r107/U148/o (1m0or02x05) 0.19 0.17 1.15 r r107/U146/o (1m0an02x05) 0.19 0.17 1.32 r r107/U144/o (1m0an02x05) 0.19 0.17 1.49 r r107/U142/o (1m0an02x05) 0.19 0.17 1.66 r r107/U140/o (1m0an02x05) 0.19 0.17 1.83 r r107/U138/o (1m0an02x05) 0.19 0.17 2.01 r r107/U136/o (1m0an02x05) 0.19 0.17 2.18 r r107/U134/o (1m0an02x05) 0.19 0.17 2.35 r r107/U132/o (1m0an02x05) 0.19 0.17 2.52 r r107/U130/o (1m0an02x05) 0.19 0.17 2.69 r r107/U128/o (1m0an02x05) 0.19 0.17 2.86 r r107/U126/o (1m0an02x05) 0.19 0.17 3.04 r r107/U124/o (1m0an02x05) 0.19 0.17 3.21 r r107/U122/o (1m0an02x05) 0.19 0.17 3.38 r r107/U120/o (1m0an02x05) 0.19 0.17 3.55 r r107/U118/o (1m0an02x05) 0.19 0.17 3.72 r r107/U116/o (1m0an02x05) 0.19 0.17 3.89 r r107/U114/o (1m0an02x05) 0.19 0.17 4.07 r r107/U112/o (1m0an02x05) 0.19 0.17 4.24 r r107/U110/o (1m0an02x05) 0.19 0.17 4.41 r r107/U108/o (1m0an02x05) 0.19 0.17 4.58 r r107/U106/o (1m0an02x05) 0.19 0.17 4.75 r r107/U104/o (1m0an02x05) 0.19 0.17 4.93 r r107/U102/o (1m0an02x05) 0.19 0.17 5.10 r r107/U100/o (1m0an02x05) 0.19 0.17 5.27 r r107/U98/o (1m0an02x05) 0.19 0.17 5.44 r r107/U96/o (1m0an02x05) 0.19 0.17 5.61 r r107/U94/o (1m0an02x05) 0.19 0.17 5.78 r r107/U92/o (1m0an02x05) 0.19 0.17 5.96 r r107/U90/o (1m0an02x05) 0.19 0.17 6.13 r r107/U88/o (1m0an02x05) 0.19 0.17 6.30 r r107/U86/o (1m0an02x05) 0.19 0.17 6.47 r r107/U84/o (1m0an02x05) 0.19 0.17 6.64 r r107/U82/o (1m0an02x05) 0.19 0.17 6.82 r r107/U80/o (1m0an02x05) 0.19 0.17 6.99 r r107/U78/o (1m0an02x05) 0.19 0.17 7.16 r r107/U76/o (1m0an02x05) 0.19 0.17 7.33 r r107/U74/o (1m0an02x05) 0.19 0.17 7.50 r r107/U72/o (1m0an02x05) 0.19 0.17 7.67 r r107/U70/o (1m0an02x05) 0.19 0.17 7.85 r r107/U68/o (1m0an02x05) 0.19 0.17 8.02 r r107/U66/o (1m0an02x05) 0.19 0.17 8.19 r r107/U64/o (1m0an02x05) 0.19 0.17 8.36 r r107/U62/o (1m0an02x05) 0.19 0.17 8.53 r r107/U60/o (1m0an02x05) 0.19 0.17 8.70 r r107/U58/o (1m0an02x05) 0.19 0.17 8.88 r r107/U56/o (1m0an02x05) 0.11 0.12 8.99 r r107/U55/o (1m0xo00x05) 0.10 0.13 9.12 r U1249/o (1m0mx22x10) 0.06 0.09 9.21 r fract_i2f_reg[47]/d (1m0ma04x05) 0.06 0.00 9.21 r data arrival time 9.21 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fract_i2f_reg[47]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.06 9.94 data required time 9.94 ----------------------------------------------------------- data required time 9.94 data arrival time -9.21 ----------------------------------------------------------- slack (MET) 0.73 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[11] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U3157/o (1m0ca03x20) 0.11 0.10 7.87 f u4/U3277/o (1m0na04x50) 0.07 0.08 7.95 r u4/U2981/o (1m0in00x30) 0.05 0.04 8.00 f u4/U2530/o (1m0mx22x20) 0.03 0.07 8.07 f u4/U3156/o (1m0an02x05) 0.06 0.08 8.16 f u4/U2850/o (1m0or03x20) 0.03 0.08 8.24 f u4/U2847/o (1m0an03x20) 0.03 0.07 8.31 f u4/U3279/o (1m0or03x40) 0.05 0.08 8.40 f u4/U2958/o (1m0in00x50) 0.05 0.05 8.45 r u4/U3054/o (1m0na02x20) 0.06 0.05 8.50 f u4/U2939/o (1m0in00x20) 0.04 0.04 8.54 r u4/U2938/o (1m0na02x20) 0.08 0.06 8.60 f u4/U3234/o (1m0co01x50) 0.09 0.08 8.68 r u4/U2948/o (1m0na02x30) 0.06 0.04 8.72 f u4/U3272/o (1m0na03x50) 0.08 0.07 8.79 r u4/U3053/o (1m0bf00x60) 0.10 0.10 8.89 r u4/U2976/o (1m0no02x30) 0.09 0.04 8.93 f u4/U3267/o (1m0bf00x100) 0.02 0.05 8.99 f U1340/o (1m0in00x10) 0.17 0.13 9.11 r U1339/o (1m0no02x10) 0.08 0.07 9.19 f fpout_reg[11]/d (1m0ma04x05) 0.08 0.00 9.19 f data arrival time 9.19 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[11]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.19 -------------------------------------------------------------------------- slack (MET) 0.73 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[4] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U2881/o (1m0ca03x05) 0.23 0.20 7.98 f u4/U2879/o (1m0na04x20) 0.13 0.14 8.11 r u4/U2342/o (1m0na04x20) 0.07 0.07 8.18 f u4/U3173/o (1m0or03x20) 0.07 0.12 8.31 f u4/U3264/o (1m0or03x20) 0.03 0.09 8.40 f u4/U2786/o (1m0na02x20) 0.05 0.04 8.44 r u4/U2782/o (1m0na03x15) 0.11 0.08 8.52 f u4/U3238/o (1m0na02x30) 0.09 0.09 8.61 r u4/U3234/o (1m0co01x50) 0.06 0.05 8.66 f u4/U2948/o (1m0na02x30) 0.06 0.05 8.72 r u4/U3272/o (1m0na03x50) 0.08 0.06 8.77 f u4/U3273/o (1m0bf00x100) 0.05 0.09 8.86 f u4/U3051/o (1m0no02x10) 0.13 0.09 8.95 r U1378/o (1m0in00x10) 0.12 0.11 9.07 f U1377/o (1m0no02x10) 0.13 0.12 9.18 r fpout_reg[4]/d (1m0ma04x05) 0.13 0.00 9.18 r data arrival time 9.18 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[4]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.18 -------------------------------------------------------------------------- slack (MET) 0.74 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[18] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U2881/o (1m0ca03x05) 0.23 0.20 7.98 f u4/U2879/o (1m0na04x20) 0.13 0.14 8.11 r u4/U2342/o (1m0na04x20) 0.07 0.07 8.18 f u4/U3173/o (1m0or03x20) 0.07 0.12 8.31 f u4/U3264/o (1m0or03x20) 0.03 0.09 8.40 f u4/U2786/o (1m0na02x20) 0.05 0.04 8.44 r u4/U2782/o (1m0na03x15) 0.11 0.08 8.52 f u4/U3238/o (1m0na02x30) 0.09 0.09 8.61 r u4/U3234/o (1m0co01x50) 0.06 0.05 8.66 f u4/U2948/o (1m0na02x30) 0.06 0.05 8.72 r u4/U3272/o (1m0na03x50) 0.08 0.06 8.77 f u4/U3273/o (1m0bf00x100) 0.05 0.09 8.86 f u4/U2979/o (1m0no02x10) 0.13 0.09 8.95 r U1352/o (1m0in00x10) 0.12 0.11 9.07 f U1351/o (1m0no02x10) 0.13 0.12 9.18 r fpout_reg[18]/d (1m0ma04x05) 0.13 0.00 9.18 r data arrival time 9.18 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[18]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.18 -------------------------------------------------------------------------- slack (MET) 0.74 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[10] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U2881/o (1m0ca03x05) 0.23 0.20 7.98 f u4/U2879/o (1m0na04x20) 0.13 0.14 8.11 r u4/U2342/o (1m0na04x20) 0.07 0.07 8.18 f u4/U3173/o (1m0or03x20) 0.07 0.12 8.31 f u4/U3264/o (1m0or03x20) 0.03 0.09 8.40 f u4/U2786/o (1m0na02x20) 0.05 0.04 8.44 r u4/U2782/o (1m0na03x15) 0.11 0.08 8.52 f u4/U3238/o (1m0na02x30) 0.09 0.09 8.61 r u4/U3234/o (1m0co01x50) 0.06 0.05 8.66 f u4/U2948/o (1m0na02x30) 0.06 0.05 8.72 r u4/U3272/o (1m0na03x50) 0.08 0.06 8.77 f u4/U3273/o (1m0bf00x100) 0.05 0.09 8.86 f u4/U3044/o (1m0no02x10) 0.13 0.09 8.95 r U1406/o (1m0in00x10) 0.12 0.11 9.07 f U1405/o (1m0no02x10) 0.13 0.12 9.18 r fpout_reg[10]/d (1m0ma04x05) 0.13 0.00 9.18 r data arrival time 9.18 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[10]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.18 -------------------------------------------------------------------------- slack (MET) 0.74 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[2] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U2881/o (1m0ca03x05) 0.23 0.20 7.98 f u4/U2879/o (1m0na04x20) 0.13 0.14 8.11 r u4/U2342/o (1m0na04x20) 0.07 0.07 8.18 f u4/U3173/o (1m0or03x20) 0.07 0.12 8.31 f u4/U3264/o (1m0or03x20) 0.03 0.09 8.40 f u4/U2786/o (1m0na02x20) 0.05 0.04 8.44 r u4/U2782/o (1m0na03x15) 0.11 0.08 8.52 f u4/U3238/o (1m0na02x30) 0.09 0.09 8.61 r u4/U3234/o (1m0co01x50) 0.06 0.05 8.66 f u4/U2948/o (1m0na02x30) 0.06 0.05 8.72 r u4/U3272/o (1m0na03x50) 0.08 0.06 8.77 f u4/U3273/o (1m0bf00x100) 0.05 0.09 8.86 f u4/U3050/o (1m0no02x10) 0.13 0.09 8.95 r U1408/o (1m0in00x10) 0.12 0.11 9.07 f U1407/o (1m0no02x10) 0.13 0.12 9.18 r fpout_reg[2]/d (1m0ma04x05) 0.13 0.00 9.18 r data arrival time 9.18 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[2]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.18 -------------------------------------------------------------------------- slack (MET) 0.74 Startpoint: fpu_op_r3_reg[2] (rising edge-triggered flip-flop clocked by clk) Endpoint: fpout_reg[9] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Trans Incr Path -------------------------------------------------------------------------- clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r3_reg[2]/ck (1m0ma04x40) 0.00 0.00 0.00 r fpu_op_r3_reg[2]/o (1m0ma04x40) 0.15 0.14 0.14 r U1392/o (1m0in00x10) 0.15 0.14 0.29 f U700/o (1m0na02x20) 0.09 0.09 0.38 r U1550/o (1m0in00x30) 0.09 0.09 0.47 f U1882/o (1m0bf00x100) 0.05 0.09 0.56 f U655/o (1m0ca03x20) 0.09 0.09 0.65 r U629/o (1m0na04x10) 0.17 0.14 0.79 f U632/o (1m0bf00x40) 0.07 0.11 0.91 f u4/U2248/o (1m0in00x50) 0.10 0.09 1.00 r u4/U3322/o (1m0na04x50) 0.06 0.05 1.05 f u4/U3242/o (1m0in01x70) 0.04 0.04 1.08 r u4/U3328/o (1m0na04x50) 0.07 0.06 1.14 f u4/U3323/o (1m0or03x40) 0.03 0.08 1.22 f u4/U3243/o (1m0in01x70) 0.03 0.03 1.25 r u4/U2055/o (1m0na04x30) 0.06 0.06 1.31 f u4/U1966/o (1m0in00x30) 0.06 0.06 1.37 r u4/U3317/o (1m0na04x50) 0.07 0.07 1.44 f u4/U3300/o (1m0or03x40) 0.04 0.09 1.53 f u4/U3319/o (1m0or03x40) 0.04 0.08 1.62 f u4/U3301/o (1m0or03x40) 0.04 0.08 1.70 f u4/U2445/o (1m0in00x50) 0.05 0.05 1.74 r u4/U3297/o (1m0na04x50) 0.07 0.07 1.81 f u4/U1573/o (1m0in00x50) 0.04 0.04 1.85 r u4/U3299/o (1m0na04x50) 0.07 0.07 1.92 f u4/U3318/o (1m0or03x40) 0.04 0.09 2.01 f u4/U1576/o (1m0in00x70) 0.04 0.04 2.05 r u4/U3296/o (1m0na04x50) 0.07 0.06 2.11 f u4/U1587/o (1m0in00x50) 0.06 0.06 2.17 r u4/U3282/o (1m0na04x50) 0.09 0.08 2.25 f u4/U3298/o (1m0or03x40) 0.04 0.10 2.35 f u4/U3016/o (1m0no03x50) 0.12 0.09 2.44 r u4/U1917/o (1m0or03x20) 0.06 0.08 2.52 r u4/U2449/o (1m0or03x20) 0.04 0.07 2.59 r u4/U3129/o (1m0bf00x60) 0.10 0.10 2.68 r u4/add_402/plus/plus/U6/o (1m0an02x05) 0.15 0.14 2.82 r u4/add_402/plus/plus/U1_1/co (1m0af00x20) 0.06 0.13 2.95 r u4/add_402/plus/plus/U1_2/co (1m0af00x20) 0.05 0.11 3.06 r u4/add_402/plus/plus/U1_3/co (1m0af00x10) 0.07 0.13 3.19 r u4/add_402/plus/plus/U1_4/co (1m0af00x10) 0.11 0.16 3.35 r u4/add_402/plus/plus/U5/o (1m0xo00x05) 0.12 0.14 3.49 f u4/sub_410/minus/minus/U12/o (1m0in00x10) 0.10 0.10 3.59 r u4/sub_410/minus/minus/U2_5/co (1m0af00x10) 0.09 0.18 3.77 r u4/sub_410/minus/minus/U2_6/co (1m0af00x20) 0.04 0.11 3.88 r u4/sub_410/minus/minus/U13/o (1m0xn00x05) 0.21 0.19 4.07 r u4/U1899/o (1m0na02x20) 0.08 0.05 4.12 f u4/U3165/o (1m0no03x50) 0.09 0.08 4.20 r u4/U3316/o (1m0or03x40) 0.04 0.07 4.27 r u4/U2208/o (1m0in00x70) 0.05 0.05 4.32 f u4/U1785/o (1m0na02x30) 0.06 0.04 4.35 r u4/U2276/o (1m0na04x10) 0.14 0.11 4.47 f u4/U2275/o (1m0na02x10) 0.12 0.12 4.58 r u4/U2060/o (1m0na04x15) 0.12 0.11 4.69 f u4/U2855/o (1m0bf00x60) 0.05 0.09 4.79 f u4/U3305/o (1m0or03x40) 0.03 0.07 4.86 f u4/U3285/o (1m0or03x40) 0.05 0.09 4.95 f u4/U3075/o (1m0bf00x60) 0.07 0.09 5.04 f u4/U2389/o (1m0in00x70) 0.05 0.05 5.09 r u4/U3215/o (1m0co05x50) 0.06 0.06 5.15 f u4/U3303/o (1m0or03x40) 0.05 0.12 5.27 f u4/U3284/o (1m0in01x180) 0.04 0.04 5.31 r u4/U3194/o (1m0co07x50) 0.08 0.06 5.37 f u4/U2379/o (1m0bf00x40) 0.04 0.07 5.44 f u4/U2292/o (1m0in00x50) 0.05 0.05 5.48 r u4/U3196/o (1m0na02x30) 0.06 0.05 5.54 f u4/U3096/o (1m0in00x30) 0.10 0.08 5.62 r u4/U3100/o (1m0bf00x60) 0.12 0.11 5.73 r u4/U2254/o (1m0ca03x30) 0.07 0.06 5.79 f u4/U2138/o (1m0co07x30) 0.19 0.14 5.93 r u4/U1668/o (1m0in00x15) 0.09 0.08 6.01 f u4/U1667/o (1m0co07x15) 0.30 0.20 6.21 r u4/U1666/o (1m0or03x20) 0.05 0.10 6.30 r u4/U2052/o (1m0na02x20) 0.06 0.04 6.35 f u4/U2048/o (1m0na04x30) 0.09 0.08 6.43 r u4/U3325/o (1m0na02x50) 0.06 0.03 6.45 f u4/U2507/o (1m0mx22x10) 0.04 0.09 6.54 f u4/U3085/o (1m0an02x10) 0.08 0.10 6.64 f u4/U2831/o (1m0co01x05) 0.32 0.25 6.89 r u4/U2405/o (1m0bf00x20) 0.12 0.14 7.03 r u4/U2435/o (1m0na04x15) 0.11 0.10 7.13 f u4/U2816/o (1m0in00x20) 0.07 0.07 7.20 r u4/U2811/o (1m0na02x05) 0.26 0.21 7.41 f u4/U2815/o (1m0in00x10) 0.22 0.21 7.61 r u4/U3089/o (1m0an02x20) 0.18 0.16 7.78 r u4/U2881/o (1m0ca03x05) 0.23 0.20 7.98 f u4/U2879/o (1m0na04x20) 0.13 0.14 8.11 r u4/U2342/o (1m0na04x20) 0.07 0.07 8.18 f u4/U3173/o (1m0or03x20) 0.07 0.12 8.31 f u4/U3264/o (1m0or03x20) 0.03 0.09 8.40 f u4/U2786/o (1m0na02x20) 0.05 0.04 8.44 r u4/U2782/o (1m0na03x15) 0.11 0.08 8.52 f u4/U3238/o (1m0na02x30) 0.09 0.09 8.61 r u4/U3234/o (1m0co01x50) 0.06 0.05 8.66 f u4/U2948/o (1m0na02x30) 0.06 0.05 8.72 r u4/U3272/o (1m0na03x50) 0.08 0.06 8.77 f u4/U3053/o (1m0bf00x60) 0.06 0.09 8.86 f u4/U2994/o (1m0no02x20) 0.12 0.09 8.95 r U1388/o (1m0in00x10) 0.07 0.06 9.02 f U1387/o (1m0no02x10) 0.12 0.10 9.12 r fpout_reg[9]/d (1m0ma04x05) 0.12 0.00 9.12 r data arrival time 9.12 clock clk (rise edge) 10.00 10.00 clock network delay (ideal) 0.00 10.00 fpout_reg[9]/ck (1m0ma04x05) 0.00 10.00 r library setup time -0.08 9.92 data required time 9.92 -------------------------------------------------------------------------- data required time 9.92 data arrival time -9.12 -------------------------------------------------------------------------- slack (MET) 0.80