**************************************** Report : constraint -all_violators -verbose Design : fpu Version: 2000.11-SP1 Date : Sun Jul 8 17:11:18 2001 **************************************** Startpoint: opa[30] (input port) Endpoint: opa_r_reg[30] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[30] (in) 0.00 0.00 f opa_r_reg[30]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[30]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.03 0.03 data required time 0.03 ----------------------------------------------------------- data required time 0.03 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: fpu_op[1] (input port) Endpoint: fpu_op_r1_reg[1] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 r fpu_op[1] (in) 0.00 0.00 r fpu_op_r1_reg[1]/d (1m0ma04x10) 0.00 0.00 r data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r1_reg[1]/ck (1m0ma04x10) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: fpu_op[2] (input port) Endpoint: fpu_op_r1_reg[2] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 r fpu_op[2] (in) 0.00 0.00 r fpu_op_r1_reg[2]/d (1m0ma04x10) 0.00 0.00 r data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r1_reg[2]/ck (1m0ma04x10) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[30] (input port) Endpoint: opb_r_reg[30] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[30] (in) 0.00 0.00 f opb_r_reg[30]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[30]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[27] (input port) Endpoint: opa_r_reg[27] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[27] (in) 0.00 0.00 f opa_r_reg[27]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[27]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[29] (input port) Endpoint: opa_r_reg[29] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[29] (in) 0.00 0.00 f opa_r_reg[29]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[29]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[28] (input port) Endpoint: opa_r_reg[28] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[28] (in) 0.00 0.00 f opa_r_reg[28]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[28]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: rmode[0] (input port) Endpoint: rmode_r1_reg[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 r rmode[0] (in) 0.00 0.00 r rmode_r1_reg[0]/d (1m0ma04x05) 0.00 0.00 r data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 rmode_r1_reg[0]/ck (1m0ma04x05) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: rmode[1] (input port) Endpoint: rmode_r1_reg[1] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 r rmode[1] (in) 0.00 0.00 r rmode_r1_reg[1]/d (1m0ma04x05) 0.00 0.00 r data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 rmode_r1_reg[1]/ck (1m0ma04x05) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[24] (input port) Endpoint: opa_r_reg[24] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[24] (in) 0.00 0.00 f opa_r_reg[24]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[24]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[26] (input port) Endpoint: opa_r_reg[26] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[26] (in) 0.00 0.00 f opa_r_reg[26]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[26]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[25] (input port) Endpoint: opa_r_reg[25] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[25] (in) 0.00 0.00 f opa_r_reg[25]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[25]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[23] (input port) Endpoint: opa_r_reg[23] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[23] (in) 0.00 0.00 f opa_r_reg[23]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[23]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[27] (input port) Endpoint: opb_r_reg[27] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[27] (in) 0.00 0.00 f opb_r_reg[27]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[27]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[25] (input port) Endpoint: opb_r_reg[25] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[25] (in) 0.00 0.00 f opb_r_reg[25]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[25]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[10] (input port) Endpoint: opa_r_reg[10] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[10] (in) 0.00 0.00 f opa_r_reg[10]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[10]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[6] (input port) Endpoint: opa_r_reg[6] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[6] (in) 0.00 0.00 f opa_r_reg[6]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[6]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[8] (input port) Endpoint: opa_r_reg[8] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[8] (in) 0.00 0.00 f opa_r_reg[8]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[8]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[20] (input port) Endpoint: opa_r_reg[20] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[20] (in) 0.00 0.00 f opa_r_reg[20]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[20]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[22] (input port) Endpoint: opa_r_reg[22] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[22] (in) 0.00 0.00 f opa_r_reg[22]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[22]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[9] (input port) Endpoint: opa_r_reg[9] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[9] (in) 0.00 0.00 f opa_r_reg[9]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[9]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[24] (input port) Endpoint: opb_r_reg[24] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[24] (in) 0.00 0.00 f opb_r_reg[24]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[24]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[26] (input port) Endpoint: opb_r_reg[26] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[26] (in) 0.00 0.00 f opb_r_reg[26]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[26]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[22] (input port) Endpoint: opb_r_reg[22] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[22] (in) 0.00 0.00 f opb_r_reg[22]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[22]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[28] (input port) Endpoint: opb_r_reg[28] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[28] (in) 0.00 0.00 f opb_r_reg[28]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[28]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[18] (input port) Endpoint: opa_r_reg[18] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[18] (in) 0.00 0.00 f opa_r_reg[18]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[18]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[5] (input port) Endpoint: opa_r_reg[5] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[5] (in) 0.00 0.00 f opa_r_reg[5]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[5]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[7] (input port) Endpoint: opa_r_reg[7] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[7] (in) 0.00 0.00 f opa_r_reg[7]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[7]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[17] (input port) Endpoint: opa_r_reg[17] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[17] (in) 0.00 0.00 f opa_r_reg[17]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[17]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[19] (input port) Endpoint: opa_r_reg[19] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[19] (in) 0.00 0.00 f opa_r_reg[19]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[19]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[21] (input port) Endpoint: opa_r_reg[21] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[21] (in) 0.00 0.00 f opa_r_reg[21]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[21]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[4] (input port) Endpoint: opa_r_reg[4] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[4] (in) 0.00 0.00 f opa_r_reg[4]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[4]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[1] (input port) Endpoint: opa_r_reg[1] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[1] (in) 0.00 0.00 f opa_r_reg[1]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[1]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[2] (input port) Endpoint: opa_r_reg[2] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[2] (in) 0.00 0.00 f opa_r_reg[2]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[2]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[3] (input port) Endpoint: opa_r_reg[3] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[3] (in) 0.00 0.00 f opa_r_reg[3]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[3]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[15] (input port) Endpoint: opa_r_reg[15] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[15] (in) 0.00 0.00 f opa_r_reg[15]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[15]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[29] (input port) Endpoint: opb_r_reg[29] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[29] (in) 0.00 0.00 f opb_r_reg[29]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[29]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[23] (input port) Endpoint: opb_r_reg[23] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[23] (in) 0.00 0.00 f opb_r_reg[23]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[23]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[7] (input port) Endpoint: opb_r_reg[7] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[7] (in) 0.00 0.00 f opb_r_reg[7]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[7]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[3] (input port) Endpoint: opb_r_reg[3] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[3] (in) 0.00 0.00 f opb_r_reg[3]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[3]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[8] (input port) Endpoint: opb_r_reg[8] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[8] (in) 0.00 0.00 f opb_r_reg[8]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[8]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[9] (input port) Endpoint: opb_r_reg[9] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[9] (in) 0.00 0.00 f opb_r_reg[9]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[9]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[10] (input port) Endpoint: opb_r_reg[10] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[10] (in) 0.00 0.00 f opb_r_reg[10]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[10]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[16] (input port) Endpoint: opb_r_reg[16] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[16] (in) 0.00 0.00 f opb_r_reg[16]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[16]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[19] (input port) Endpoint: opb_r_reg[19] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[19] (in) 0.00 0.00 f opb_r_reg[19]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[19]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[20] (input port) Endpoint: opb_r_reg[20] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[20] (in) 0.00 0.00 f opb_r_reg[20]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[20]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[21] (input port) Endpoint: opb_r_reg[21] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[21] (in) 0.00 0.00 f opb_r_reg[21]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[21]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[1] (input port) Endpoint: opb_r_reg[1] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[1] (in) 0.00 0.00 f opb_r_reg[1]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[1]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[2] (input port) Endpoint: opb_r_reg[2] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[2] (in) 0.00 0.00 f opb_r_reg[2]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[2]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[4] (input port) Endpoint: opb_r_reg[4] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[4] (in) 0.00 0.00 f opb_r_reg[4]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[4]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[13] (input port) Endpoint: opb_r_reg[13] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[13] (in) 0.00 0.00 f opb_r_reg[13]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[13]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[14] (input port) Endpoint: opb_r_reg[14] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[14] (in) 0.00 0.00 f opb_r_reg[14]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[14]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[15] (input port) Endpoint: opb_r_reg[15] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[15] (in) 0.00 0.00 f opb_r_reg[15]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[15]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[5] (input port) Endpoint: opb_r_reg[5] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[5] (in) 0.00 0.00 f opb_r_reg[5]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[5]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[12] (input port) Endpoint: opb_r_reg[12] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[12] (in) 0.00 0.00 f opb_r_reg[12]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[12]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[17] (input port) Endpoint: opb_r_reg[17] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[17] (in) 0.00 0.00 f opb_r_reg[17]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[17]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[6] (input port) Endpoint: opb_r_reg[6] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[6] (in) 0.00 0.00 f opb_r_reg[6]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[6]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[18] (input port) Endpoint: opb_r_reg[18] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[18] (in) 0.00 0.00 f opb_r_reg[18]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[18]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[11] (input port) Endpoint: opb_r_reg[11] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[11] (in) 0.00 0.00 f opb_r_reg[11]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[11]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[13] (input port) Endpoint: opa_r_reg[13] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[13] (in) 0.00 0.00 f opa_r_reg[13]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[13]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[16] (input port) Endpoint: opa_r_reg[16] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[16] (in) 0.00 0.00 f opa_r_reg[16]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[16]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[11] (input port) Endpoint: opa_r_reg[11] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[11] (in) 0.00 0.00 f opa_r_reg[11]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[11]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[12] (input port) Endpoint: opa_r_reg[12] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[12] (in) 0.00 0.00 f opa_r_reg[12]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[12]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[14] (input port) Endpoint: opa_r_reg[14] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[14] (in) 0.00 0.00 f opa_r_reg[14]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[14]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[0] (input port) Endpoint: opa_r_reg[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[0] (in) 0.00 0.00 f opa_r_reg[0]/d (1m0ma04x40) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[0]/ck (1m0ma04x40) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[0] (input port) Endpoint: opb_r_reg[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[0] (in) 0.00 0.00 f opb_r_reg[0]/d (1m0ma04x20) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[0]/ck (1m0ma04x20) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opa[31] (input port) Endpoint: opa_r_reg[31] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opa[31] (in) 0.00 0.00 f opa_r_reg[31]/d (1m0ma04x20) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opa_r_reg[31]/ck (1m0ma04x20) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: opb[31] (input port) Endpoint: opb_r_reg[31] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f opb[31] (in) 0.00 0.00 f opb_r_reg[31]/d (1m0ma04x20) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 opb_r_reg[31]/ck (1m0ma04x20) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02 Startpoint: fpu_op[0] (input port) Endpoint: fpu_op_r1_reg[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Des/Clust/Port Wire Load Model Library ------------------------------------------------ fpu unit_wl cwl Point Incr Path ----------------------------------------------------------- clock (input port clock) (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 input external delay 0.00 0.00 f fpu_op[0] (in) 0.00 0.00 f fpu_op_r1_reg[0]/d (1m0ma04x20) 0.00 0.00 f data arrival time 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 fpu_op_r1_reg[0]/ck (1m0ma04x20) 0.00 0.00 r library hold time 0.02 0.02 data required time 0.02 ----------------------------------------------------------- data required time 0.02 data arrival time 0.00 ----------------------------------------------------------- slack (VIOLATED) -0.02