/************************** Read in design ****************************/
/* Design Compiler Shell script
 */
remove_design -all
define_design_lib work -path ../mra
analyze -library work -format vhdl ../hdl/add_sub27_arch.vhd
analyze -library work -format vhdl ../hdl/div_r2_arch.vhd
analyze -library work -format vhdl ../hdl/mul_r2_arch.vhd
analyze -library work -format vhdl ../hdl/except_arch.vhd
analyze -library work -format vhdl ../hdl/pre_norm_fmul_arch.vhd
analyze -library work -format vhdl ../hdl/pre_norm_arch.vhd
analyze -library work -format vhdl ../hdl/post_norm_arch.vhd
analyze -library work -format vhdl ../hdl/fpu_arch.vhd

elaborate -library work fpu

write -format db -hier -output fpu_pre.db

read 1m0_typ.db

read fpu_pre.db

set_dont_use 1m0_typ/1m0la*
set_dont_use 1m0_typ/1m0xs*
set_dont_use 1m0_typ/1m0xa*
set_dont_use 1m0_typ/1m0ms*
set_dont_use 1m0_typ/1m0ma33*
set_dont_use 1m0_typ/1m0ya*
set_dont_use 1m0_typ/1m0sl*

link

current_design "fpu"
create_clock -name "clk" -period 10 -waveform { 0.000000 5.0000 } find(port, {"clk"})

set_operating_conditions WCCOM
set_wire_load_mode top
set_wire_load_model -library cwl -name unit_wl 

check_design > fpu + "_check_design.rpt"

uniquify

compile -map_effort high

write -format verilog -hierarchy -output fpu + "_hier.v"

ungroup -all -flatten
write -format db -hierarchy -output fpu + ".db"

write -format verilog  -hierarchy -output fpu + ".v"

report_cell > fpu + "_cell.rpt"

report_constraints -all -v > fpu + "_constraints_violators.rpt"

report_timing -loops -max_paths 100 > fpu + "_loop.rpt"

report_timing -tran -delay max -max_paths 20 -nworst 1 -nosplit > fpu + "_timing.rpt"

quit