Warning: Design 'fpu_pre.db:except' comes before design 'except.db:except' in the link_library; 'except.db:except' will be ignored. (UIO-92)
Information: Design 'except' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:pre_norm' comes before design 'pre_norm.db:pre_norm' in the link_library; 'pre_norm.db:pre_norm' will be ignored. (UIO-92)
Information: Design 'pre_norm' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:pre_norm_fmul' comes before design 'pre_norm_fmul.db:pre_norm_fmul' in the link_library; 'pre_norm_fmul.db:pre_norm_fmul' will be ignored. (UIO-92)
Information: Design 'pre_norm_fmul' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:add_sub27' comes before design 'add_sub27.db:add_sub27' in the link_library; 'add_sub27.db:add_sub27' will be ignored. (UIO-92)
Information: Design 'add_sub27' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:mul_r2' comes before design 'mul_r2.db:mul_r2' in the link_library; 'mul_r2.db:mul_r2' will be ignored. (UIO-92)
Information: Design 'mul_r2' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:div_r2' comes before design 'div_r2.db:div_r2' in the link_library; 'div_r2.db:div_r2' will be ignored. (UIO-92)
Information: Design 'div_r2' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: Design 'fpu_pre.db:post_norm' comes before design 'post_norm.db:post_norm' in the link_library; 'post_norm.db:post_norm' will be ignored. (UIO-92)
Information: Design 'post_norm' is referenced in design 'fpu_pre.db:fpu'. (UIO-93)
Warning: In design 'fpu', a pin on submodule 'u6' is connected to logic 1 or logic 0. (LINT-32)
   Pin 'opa[25]' is connected to logic 0. 
   Pin 'opa[24]' is connected to logic 0. 
   Pin 'opa[23]' is connected to logic 0. 
   Pin 'opa[22]' is connected to logic 0. 
   Pin 'opa[21]' is connected to logic 0. 
   Pin 'opa[20]' is connected to logic 0. 
   Pin 'opa[19]' is connected to logic 0. 
   Pin 'opa[18]' is connected to logic 0. 
   Pin 'opa[17]' is connected to logic 0. 
   Pin 'opa[16]' is connected to logic 0. 
   Pin 'opa[15]' is connected to logic 0. 
   Pin 'opa[14]' is connected to logic 0. 
   Pin 'opa[13]' is connected to logic 0. 
   Pin 'opa[12]' is connected to logic 0. 
   Pin 'opa[11]' is connected to logic 0. 
   Pin 'opa[10]' is connected to logic 0. 
   Pin 'opa[9]' is connected to logic 0. 
   Pin 'opa[8]' is connected to logic 0. 
   Pin 'opa[7]' is connected to logic 0. 
   Pin 'opa[6]' is connected to logic 0. 
   Pin 'opa[5]' is connected to logic 0. 
   Pin 'opa[4]' is connected to logic 0. 
   Pin 'opa[3]' is connected to logic 0. 
   Pin 'opa[2]' is connected to logic 0. 
   Pin 'opa[1]' is connected to logic 0. 
   Pin 'opa[0]' is connected to logic 0. 
Warning: In design 'fpu', the same net is connected to more than one pin on submodule 'u6'. (LINT-33)
   Net 'out_fixed[21]' is connected to pins 'opa[25]', 'opa[21]', 'opa[12]', 'opa[16]', 'opa[8]', 'opa[1]', 'opa[24]', 'opa[23]', 'opa[19]', 'opa[14]', 'opa[7]', 'opa[5]', 'opa[10]', 'opa[3]', 'opa[22]', 'opa[18]', 'opa[11]', 'opa[2]', 'opa[17]', 'opa[15]', 'opa[6]', 'opa[20]', 'opa[13]', 'opa[4]', 'opa[9]', 'opa[0]'. 
Warning: In design 'div_r2', port 'opb[23]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[22]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[21]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[20]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[19]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[18]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[17]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[16]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[15]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[14]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[13]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[12]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[11]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[10]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[9]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[8]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[7]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[6]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[5]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[4]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[3]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[2]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[1]' is not connected to any nets. (LINT-28)
Warning: In design 'div_r2', port 'opb[0]' is not connected to any nets. (LINT-28)
Warning: In design 'except', port 'opa[31]' is not connected to any nets. (LINT-28)
Warning: In design 'except', port 'opb[31]' is not connected to any nets. (LINT-28)
Warning: In design 'pre_norm_fmul', input port 'opa[22]' is connected directly to output port 'fracta[22]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[21]' is connected directly to output port 'fracta[21]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[20]' is connected directly to output port 'fracta[20]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[19]' is connected directly to output port 'fracta[19]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[18]' is connected directly to output port 'fracta[18]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[17]' is connected directly to output port 'fracta[17]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[16]' is connected directly to output port 'fracta[16]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[15]' is connected directly to output port 'fracta[15]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[14]' is connected directly to output port 'fracta[14]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[13]' is connected directly to output port 'fracta[13]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[12]' is connected directly to output port 'fracta[12]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[11]' is connected directly to output port 'fracta[11]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[10]' is connected directly to output port 'fracta[10]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[9]' is connected directly to output port 'fracta[9]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[8]' is connected directly to output port 'fracta[8]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[7]' is connected directly to output port 'fracta[7]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[6]' is connected directly to output port 'fracta[6]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[5]' is connected directly to output port 'fracta[5]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[4]' is connected directly to output port 'fracta[4]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[3]' is connected directly to output port 'fracta[3]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[2]' is connected directly to output port 'fracta[2]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[1]' is connected directly to output port 'fracta[1]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opa[0]' is connected directly to output port 'fracta[0]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[22]' is connected directly to output port 'fractb[22]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[21]' is connected directly to output port 'fractb[21]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[20]' is connected directly to output port 'fractb[20]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[19]' is connected directly to output port 'fractb[19]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[18]' is connected directly to output port 'fractb[18]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[17]' is connected directly to output port 'fractb[17]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[16]' is connected directly to output port 'fractb[16]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[15]' is connected directly to output port 'fractb[15]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[14]' is connected directly to output port 'fractb[14]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[13]' is connected directly to output port 'fractb[13]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[12]' is connected directly to output port 'fractb[12]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[11]' is connected directly to output port 'fractb[11]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[10]' is connected directly to output port 'fractb[10]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[9]' is connected directly to output port 'fractb[9]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[8]' is connected directly to output port 'fractb[8]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[7]' is connected directly to output port 'fractb[7]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[6]' is connected directly to output port 'fractb[6]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[5]' is connected directly to output port 'fractb[5]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[4]' is connected directly to output port 'fractb[4]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[3]' is connected directly to output port 'fractb[3]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[2]' is connected directly to output port 'fractb[2]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[1]' is connected directly to output port 'fractb[1]'. (LINT-29)
Warning: In design 'pre_norm_fmul', input port 'opb[0]' is connected directly to output port 'fractb[0]'. (LINT-29)
Warning: In design 'post_norm', port 'clk' is not connected to any nets. (LINT-28)