PROJECTS FOR YEAR 2001.

1. Project 1. Image processing for a robot.
   This project is to design a convolution processor and implement it in FPGAs. It will be used on a combination of two boards for a small walking robot. This is a real-life project. Processors like this are being designed by several companies. Continuation of the two projects from 1999, 2000.
   This is a strictly VHDL project.
   
   
   
2. Project 2. Dual-Processor Cube Calculus Machine.
   This project is to complete design of a dual-processor architecture for pattern recognition. Test, logic synthesis to FPGAs. This is a huge project, but excellent work was done last year by an Intel group. Real life project. Collaboration with ATR in Japan. Continuation of the many projects since 1997, and especially 2000 project.
   This is a strictly VHDL project.
   
   
   
3. Project 3. Hardware Functional Decomposer.
   This is a new idea to design hardware to decompose binary functions. Software to hardware transition. Publishable and new. You can re-use design of previous students, but it was not great. I have ideas how it can be improved.
   This is a strictly VHDL project.
   
   
   
4. Project 4. Three-dimensional Reversible Logic Hough Transform Processor. Anas (Andie) Al-Rabadi - leader.
   Hough Transform is the main method used in industrial image processing and robotics. Many new variants exist, recently published. Talks to Anas about Reversible Logic, he knows what to do. Collect literature about reversible logic (my WWW page) and Hough Transform - ask Anas.
   This is a VHDL project but you have to learn about reversible logic. VHDL used only for simulation and test, not synthesis.
   
   
   
5. Project 5. Reversible Logic Microprocessor.
   This project is to design a standard microprocessor with a very simple list of instructions but that will use reversible logic. This means, that you will have to design the cells and logic by hand, because no tools exist for reversible logic yet. The design will be only simulated. Good advanced research topic.
   This is a VHDL project but you have to learn about reversible logic. VHDL used only for simulation and test, not synthesis.
   
   
   
6. Project 6. DEC PERLE BOARD.
   This project requires some "system administration" experience. In addition to VHDL which will be rather easy, you will have to learn the operating system environment of an industrial emulator. Then, you will down-load the previous student design to this emulator.
   This is a VHDL project but you have to learn about software environment of the board. This will expose you to practical industrial large FPGA emulators. This project is difficult, but I will give credit for any partial success.