You are encouraged to send me more questions by email.
This way, when I answer them, more people will find my answers useful.
Talk to me on your homework/project ideas.
QUESTIONS ASKED
Professor Marek Perkowski
Question 1.1.:
Where I can find more on the graphical subtraction method that
you illustrated on just one example in the class?
Answer 1.1.:
I will bring the textbook that I am writing to the class on Tuesday.
I have only one copy, so if more people are interested, please share it.
Try to solve more examples and show me.
Question 1.2.:
I was in Copyman and they do not have your VHDL class notes. What shall I do?
Answer 1.2.:
I am sorry, I should write "SmartCopy", not "Copyman".
Their addres is now on my Web Page for VHDL, the same place where the wrong addres was before.
PSU Reserve Library has no longer the copy of VHDL notes.
Question 1.3.:
In my Homework 1, I have designed a sorter for 16 numbers. Is it OK?
Answer 1.3.:
For this homework it is OK, but still if you have time, I will be more happy
to see a solutions with arbitrary numbers of bits (k) and words (n).
Try to write a parametrized description with parameters "k" and "n".
Then, by substituting numerical values instead "k" and "n" you would be
able to generate immediately ARBITRARY sorters.
This is an elegant use of VHDL.
In general, what I am saying here is that if you do everything correctly, you get a grade of A.
Moreover, if you do everything correctly, PLUS you demonstrate some
interesting idea or a more general description,
you get the grade of A+ or even A++.
You can get a final grade of A+ in this class.
Question 1.4.:
I am done with Homework 1, and my simulation is OK, can I do something more for a better grade?
Answer 1.4.:
First check your simulation on more data, for instance with the same numbers repeated.
Write a good report and document in your report what you have done.
Create a good WWW Page for this class and add Homework 1 to it.
In addition, write about your experience and what you expect to learn in this class on your WWW Page.
If you will still have time before the deadline, I recommend you to do the following:
a) continue towards design using logic synthesis.
b) Extend your project towards Homework 2, or start working on Homework 2.
Question 1.5.:
I called Xilinx and they told me that the Xilinx Student Edition that I purchased from
PSU Bookstore is now obsolete and has bugs.
Answer 1.5.:
It is true that there is very recently a new edition.
It was not around when I ordered the old edition for PSU Bookstore.
Talk to PSU Bookstore about the exchange.
However, the old one also works, so do not despair if they will not agree to exchange.
We used the old one last year, and there were no significant troubles.
Question 2.1.:
I am an OCATE student. How can I get an account at PSU?
Answer 2.1.:
Please send email to support@ee.pdx.edu and tell them your name and social security
and that you are a registered student in my 510 VHDL class.
Ask for accounts for both Unix (Mentor, Cypress) and PC Network (Cypress, Xilinx, Altera, Summit).
They will assign you an account. You need email address. If you do not, you have to
contact them in person, in building FAB. Look to ECE WWW Page how to contact them in person.
Question 2.2.:
From: Wayne Robson
Dr. Perkowski:
I wanted to take a minute of yor time to ask a few questions about your VHDL
class and associated homework & projects. Given my current work load, I
feel that it would be difficult for me to work in one of the small groups
and would prefer to work alone. I also have some experience creating VHDL
designs and feel that I have mastered many of the fundamental language
constructs. I am eager to gain experience in VHDL design and feel that I
would benefit more from exploring more advanced features of the language and
a larger design. With your permission, I would like to work on a project of
my own design. I also feel that the homework projects would detract from
its completion. Perhaps, I could submit portions of this project in
substitution of the homework to demonstrate project progress and indicate
some level of competency with the appropriate language constructs.
Ultimately, this project could be made available to students and would
perhaps help them gain insight into organizing a larger design and provide
additional examples of various language constructs etc.
I have attached a visio drawing of the project concept and will provide the
following brief description. The device is what I have called a display
rendering engine. The device has a microprocessor interface which allows
access to both the internal registers and a SDRAM frame buffer memory. The
frame buffer is large enough to hold a full video frame of XGA resolution,
16 bits per pixel. The data is then read out of the frame buffer and
formatted for a digital display device such as a LCD. If you were to add a
DAC to the output of this device, it would conceptually resemble a PC video
card.
Page 1 of the visio drawing shows the top level of the design and simulation
environment. The 5307 bus functional model is a design that I am presently
working on. It reads in a file which contains certain parameters including,
number of wait states to insert in a bus cycle, active areas for the chip
select lines, etc. I am writing procedures to generate typical bus cycles,
ie read_word() and write_word(). These can then be executed in sequence and
with the appropriate parameters to provide device initialization. The panel
bench is one that I will be utilizing from our ASIC groups test bench code.
It frames the incoming data and writes it to a bitmap file for later
inspection. I will be using a synopsis smart model for the SDRAM
simulation.
Page 2 shows the block diagram of the device itself. This shows the major
data paths within the device and the primary functional blocks.
So, with your permission I would like to continue to develop this design for
my class homework/ project. Thanks.
Wayne Robson
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Answer 2.2.:
Dear Wayne,
I agree that you will work on your project for this class.
This will replace Homeworks 1, 2 and the Project.
I will put your project proposal to my WWW Page and may be somebody
would like to work with you.
If not, you will work alone.
Please create a complete WWW page with your drawings and more complete
explanation of the project for other interested students.
Many PSU students wanted to work with somebody from industry who has already some experience.
Question 2.3.:
What about the special meetings to discuss projects and review basic design?
Answer 2.3.:
The meetings will be on Thursdays at 3 p.m. in the same room as the class.
Everybody is welcome. First meeting will be next week.
Question 2.4.:
Sajjad I Pagarkar
To: Marek Perkowski
CC: sadik@e.pdx.edu, deepam@ee.pdx.edu
Dr. Perkowski,
Yesterday, me and my partners unsuccessfully tried to figure out "How do
we declare multidimensional inputs in entity declarations"?. Though we are
comfortable application of generate statement for iterative data
processing, we would appreciate if you inform us "How do we apply it for
multidimensional data array"?
Answer 2.4.:
You do not need to declare multidimensional inputs and outputs in entity.
Have one-dimensional signals in entity and another multidimensional inside
the architecture.
I will show examples of multidimensional arrays in architecture.
We never needed them in entity, but it may be possible, check VHDL language manual.
Question 2.5.:
From: "Smith, Russell H"
Dear Mr. P.
I looked around on your web page just now and I cannot find electronic
copies of the materials you showed on the overhead projector last tuesday in
VHDL class. Are these only available in hardcopy from SmartCopy or are they
located somewhere on the web and I am just too clumsy to find them? Thanks
for the help.
Answer 2.5.:
They are at the very beginning, try always to click into any underlined text,
it includes always a link to more information.