GRADING OF THE VHDL CLASS


This year, homeworks are the same as mini-projects in the past.

  1. Homework 1: quality of report = 5 %
  2. Homework 1: quality of presentation = 5 %
  3. Homework 1 quality of VHDL/VERILOG code 5 %
    TOTAL = 15 %

  4. Homework 2: quality of report 5 %
  5. Homework 2: quality of presentation 5%
  6. Homework 2: quality of VHDL/VERILOG code 10%
    TOTAL = 20 %
    TOTAL HOMEWORKS = 35 %

  7. Project: quality of presentation 1: 5 %
  8. Project: quality of presentation 2: 10%
  9. Project: quality of intermediate report: 10%
  10. Project: quality of final report: 20%
  11. Project: quality of VHDL/VERILOG code 20%
    TOTAL PROJECT = 65 %