FIBONACCI MACHINE
From HONGFEI WU
**************************************************************************************
This is updated homework #2 for Fibonacci.
Some change was done on previous one.
Now it workes well and comes out with simulation result.
Here is some description for this program.
Fibo_Dpath is the DATAPATH for the design.
The inputs are A, B and CLK.
A and B is the initial value for this Fibonacci machine with value 0 and 1 respectly.
The output thismachine is "Fibo_out" which generates values 1,2,3,5,8,13.......
There are several connect signal between DATAPATH and the CONTROL UNIT.
They are pre_P0, pre_C0, pre_C1 and pre_C2 which can be checked during simulation.
The pre_P0 is the signal which is generated by the comparator.
When A < maximum_length (11111111), CU
generates pre_C1 for ADDER to add the value A and B, and assign to Fibo_out.
Then CU generates pre_C2 for shifting B to A, finally generates
pre_C0 for shifting Fibo_out to B. When A = maximum_length, pre_P0=0, machine stops.
***********************************************************************************
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
--DATAPATH
--Fibo_Dpath Entity Description
entity Fibo_Dpath is
port( A,B: buffer qsim_state_vector(0 to 7);
CLK: in qsim_state;
Fibo_out: inout qsim_state_vector(0 to 7):="00000000");
end Fibo_Dpath;
--Fibo_Dpath Architecture Description
architecture Fibo of Fibo_Dpath is
component Fibonacci_Controller
port(P0,CLK: in qsim_state;
C0,C1,C2: out qsim_state);
end component;
component register_fibo
port(DIN_OUT: buffer qsim_state_vector(0 to 7);
DIN: in qsim_state_vector(0 to 7);
CC: in qsim_state);
end component;
component Fibo_adder
port(A,B: in qsim_state_vector(0 to 7);
CLK, Ctl: in qsim_state;
AD_OUT: inout qsim_state_vector(0 to 7);
carry: out qsim_state);
end component;
component comparator
port(A,B: in qsim_state_vector(0 to 7);
GT: out qsim_state);
end component;
signal pre_C0,pre_C1,pre_C2: qsim_state:='0';
signal pre_P0, pre_carry: qsim_state:='0';
signal maximum_length: qsim_state_vector(0 to 7):="11111111";
begin
U0: comparator port map (A, maximum_length, pre_P0);
U1: Fibonacci_Controller port map (pre_P0,CLK,pre_C0,pre_C1,pre_C2);
U2: register_fibo port map (A,B,pre_C2);
U3: register_fibo port map (B,Fibo_out,pre_C0);
U4: Fibo_adder port map (A,B, CLK,pre_C1,Fibo_out, pre_carry);
end Fibo;
library mgc_portable,WORK;
Use mgc_portable.qsim_logic.all;
use WORK.all;
-- Fibonacci_Controller Entity Description
entity Fibonacci_Controller is
port(P0,CLK: in qsim_state;
C0,C1,C2: out qsim_state);
end Fibonacci_Controller;
-- Fibonacci_Controller Architecture Description
-- The Controller realize the following relations:
-- Q1'=Q2*P0+Q1*P0BAR
-- Q2'=Q1BAR*Q2BAR*P0+Q1BAR*Q2*P0
-- C0=Q1*Q2BAR*P0
-- C1=Q1BAR*Q2BAR*P0
-- C2=Q1BAR*Q2*P0
architecture controller of Fibonacci_Controller is
signal DD1,DD2,pre_C0 : qsim_state:='0';
signal pre_C1 : qsim_state:='0';
signal pre_C2 : qsim_state:='0';
signal QQ1,QQ2: qsim_state:='0';
signal QQ1BAR,QQ2BAR: qsim_state:='1';
component Flip_Flop
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end component;
begin
Fibonacci_Controller_Process: process(P0, QQ1, QQ2)
begin
DD1<=((QQ2 and P0) or (QQ1 and (not P0)));
DD2<=(((not QQ1) and (not QQ2)and P0) or ((not QQ1) and QQ2 and P0));
pre_C0<=(QQ1 and (not QQ2) and P0);
pre_C1<=((not QQ1) and (not QQ2) and P0);
pre_C2<=((not QQ1) and QQ2 and P0);
end process Fibonacci_Controller_process;
U1: Flip_Flop port map(DD1,CLK,QQ1,QQ1BAR);
U2: Flip_Flop port map(DD2,CLK,QQ2,QQ2BAR);
-- Assign outputs
C0 <= pre_C0;
C1 <= pre_C1;
C2 <= pre_C2;
end controller;
*************************************************************************************
library mgc_portable;
use mgc_portable.qsim_logic.all;
--compar value A and maximum_lengeh, when A < maximum_lengeh,machine star.
--when A= maximum_lengeh, machine stop.
-- Fibo_comp Entity Description
entity Fibo_comp is
port(
A,B: in qsim_state_vector(0 to 7);
GT: out qsim_state
);
end Fibo_comp;
-- Fibo_comp Architecture Description
architecture BEHAVIOR of Fibo_comp is
begin
COMPARATOR_process: process(A,B)
begin
-- A < B
GT <= (A < B);
end process COMPARATOR_process;
end BEHAVIOR;
*************************************************************************************
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- Flip_Flop Entity Description
entity Flip_Flop is
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end Flip_Flop;
-- Flip_Flop Architecture Description
architecture rtl of Flip_Flop is
signal pre_Q : qsim_state:='0';
begin
FLIP_FLOP_Process: process(CLK)
begin
if (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
pre_Q <= D;
end if;
end process FLIP_FLOP_Process;
-- Assign outputs
Q <= pre_Q;
QBAR <= (not pre_Q);
end rtl;
*************************************************************************************
library mgc_portable;
use mgc_portable.qsim_logic.all;
--ADDER addes value A and B
entity Fibo_adder is
port(A,B: in qsim_state_vector(0 to 7);
CLK,Ctl: in qsim_state;
AD_OUT: inout qsim_state_vector(0 to 7);
carry: out qsim_state);
end Fibo_adder;
architecture BEHAVIOR of Fibo_adder is
signal add_out: qsim_state_vector(7 downto 0);
begin
ADD_PROCESS: process(Ctl)
variable C: qsim_state:='0';
variable AA,BB,SS: qsim_state_vector(7 downto 0);
begin
if (Ctl ='1')then
AA:=A;
BB:=B;
for i in 0 to 7 loop
SS(i):=(AA(i) xor BB(i)) xor C;
C:=((AA(i) and BB(i)) or (AA(i) and C) or (BB(i) and C));
end loop;
carry<=C;
add_out <= SS;
end if;
end process ADD_PROCESS;
KEEP_AD_BLK: BLOCK((CLK = '0') and (Ctl = '1'))
begin
AD_OUT <= guarded AD_OUT when Ctl = '0' else add_out;
end BLOCK KEEP_AD_BLK;
end BEHAVIOR;
*************************************************************************************
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- register_fibo Entity Description
entity register_fibo is
port(
DIN_OUT: buffer qsim_state_vector(7 downto 0);
DIN: in qsim_state_vector(7 downto 0);
CC: in qsim_state
);
end register_fibo;
-- regiter_fibo Architecture Description
architecture BEHAVIOR of register_fibo is
begin
REG_BLOCK: BLOCK(CC='1')
begin
DIN_OUT <= guarded DIN_OUT when CC='0' else DIN;
end BLOCK REG_BLOCK;
end BEHAVIOR;
**************************************************************************************
ANOTHER VARIANT:
ZHI WANG
FIBONACCI
--
-- The result wavefore will be send to you in file named result;
-- Following is the VHDL code for Fibonacci function
-- It contains 3 parts : the datapath, the controller, the delay component;
--This is whole processor of Fibonaci
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
--This is entity description
entity assem3 is
port( clock: in qsim_state;
zz: out qsim_state_vector(0 to 7));
end assem3;
-- architecture description
architecture behavior of assem3 is
signal cca,ccb,ccc,ccd: qsim_state;
signal pp1: qsim_state;
signal clk: qsim_state;
component fibo_contl2
port( clock: in qsim_state;
p1: in qsim_state;
ca, cb,cc, cd: out qsim_state);
end component;
component dpath2
port (ca,cb,cc, cd: in qsim_state;
clock: in qsim_state;
carry: out qsim_state;
zz: out qsim_state_vector(0 to 7));
end component;
component delay
port( clock: in qsim_state;
clko: out qsim_state);
end component;
begin
U1: delay
port map (clock,clk);
U2: fibo_contl2
port map(clk,pp1,cca,ccb,ccc,ccd);
U3: dpath2
port map(cca,ccb,ccc,ccd,clock,pp1,zz);
end behavior;
--This is datapath of fibonacci process
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
--entity description
entity dpath2 is
port ( ca,cb,cc,cd: in qsim_state;
clock : in qsim_state;
carry: out qsim_state;
zz : out qsim_state_vector(0 to 7));
end dpath2;
--architecture description of datapath
architecture behavior of dpath2 is
signal car : qsim_state;
signal X: qsim_state_vector(0 to 7):="00000001";
signal Y: qsim_state_vector(0 to 7):="00000000";
signal xx,yy, ss: qsim_state_vector(0 to 7);
component add8
port( aa,bb: in qsim_state_vector(0 to 7);
clock: in qsim_state;
conl: in qsim_state;
sum: out qsim_state_vector(0 to 7);
carry: out qsim_state );
end component;
component regst
port( clock: in qsim_state;
conl1,conl2: in qsim_state;
xx1,xx2: in qsim_state_vector(0 to 7);
yy: out qsim_state_vector(0 to 7));
end component;
begin
U1:regst
port map(clock,ca,cd,X,ss,xx);
U2:regst
port map(clock,ca,cc,Y,xx,yy);
U3:add8
port map( xx,yy,clock,cb,ss,car);
-- output assignment
zz <= ss;
carry<= car;
end behavior;
--This is the controller of Fibonacci processor
-- Input is clock;
-- Output is c1,c2,c3,c4;
--
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Bellow is the entity of controller
entity FIBO_CONTL2 is
port ( clock: in qsim_state;
p1: in qsim_state;
ca,cb,cc,cd: out qsim_state);
end FIBO_CONTL2;
architecture BEHAVIOR of FIBO_CONTL2 is
signal q1,q2: qsim_state:='0';
signal qn2,qn1: qsim_state:='1';
signal d1, d2: qsim_state;
component Flip_Flop
port( clk, D: in qsim_state;
Q, Qn: out qsim_state);
end component;
begin
controller : process
begin
wait on clock;
if (clock'event and (clock = '1') and (clock'last_value = '0')) then
d1 <= (q1 and qn2) or ( not p1 and qn1 and q2 );
d2 <= q1 or qn2;
ca <= qn1 and qn2;
cb <= qn1 and q2 ;
cc <= q1 and qn2;
cd <= q1 and q2 ;
end if;
wait for 5ns;
end process;
next_s: process
begin
wait until clock'event and clock='1';
q1<=d1;
qn1<= not d1;
q2<= d2;
qn2<= not d2;
end process;
end BEHAVIOR ;
--This is entity for register controll
library mgc_portable;
use mgc_portable.qsim_logic.all;
entity regst is
port( clock: in qsim_state;
conl1,conl2: in qsim_state;
xx1,xx2: in qsim_state_vector(0 to 7);
yy: out qsim_state_vector(0 to 7));
end regst;
architecture behavior of regst is
begin
regst :process
begin
wait until clock'event and clock ='1';
if ( conl1='1')then
yy<= xx1;
elsif(conl2='1')then
yy<=xx2;
end if;
end process;
end behavior;
--This is a adder entity for 8-bit vector
library mgc_portable;
use mgc_portable.qsim_logic.all;
entity add8 is
port ( aa,bb: in qsim_state_vector(0 to 7);
clock: in qsim_state;
conl: in qsim_state;
sum: out qsim_state_vector(0 to 7);
carry: out qsim_state );
end add8;
architecture behavior of add8 is
begin
process
variable ca : qsim_state:='0';
variable xx,yy,ss: qsim_state_vector(7 downto 0);
begin
wait until clock'event and clock ='1';
xx:=aa;
yy:=bb;
wait until clock'event and clock='1';
if (conl='1')then
for i in 0 to 7 loop
ss(i) := (xx(i) xor yy(i)) xor ca;
ca := ((xx(i) and yy(i)) or (xx(i) and ca) or (yy(i) and ca));
end loop;
end if;
wait until clock'event and clock ='1';
carry <= ca;
sum<=ss;
end process;
end behavior;
--this is a entity of clock delay
library mgc_portable;
use mgc_portable.qsim_logic.all;
entity delay is
port( clock: in qsim_state;
clko: out qsim_state);
end delay;
architecture behavior of delay is
signal dd: qsim_state;
begin
process
begin
wait until clock'event and clock ='1';
clko<= '0';
for i in 0 to 1 loop
wait until clock'event and clock='1';
end loop;
clko<='1';
for i in 0 to 1 loop
wait until clock'event and clock='1';
end loop;
end process;
end behavior;