CAT policies.
From Sida Zhou, Vaughn Zechmann, Zhiw Wang, Hongfei Wu.
Organization PSU
Date 1995
This is partial codes of the Unate function project, The code
is try to implement the Quine_McCluskey methods in a parallel fashion
by define each process hold one term, The term is hold is such a
order that each process only differ in one positive literal. SO that
the process only need to get imformation from it right. but due to time
constrains, We have not be able to finish it, but all the code code here
compiled and partially simulated. if we have time, we will continune this
project.
------------------------------------------------------------------------
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
USE WORK.ALL;
entity unate_machine is
port( CLK: in qsim_state;
COUT: out qsim_state_vector(15 downto 0)
);
end unate_machine;
architecture behavior of unate_machine is
USE WORK.Quine_McCluskey_def.ALL;
signal P0,P1,P2,P3,P4,P5: qsim_state:='0';
signal OP_CODE: qsim_state_vector(2 downto 0):="000";
component paralell_process
port( CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0);
COUT: out qsim_state_vector(15 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end component;
component unate_ctr
port( P0,P1,P2,P3,P4,P5,CLK: in qsim_state;
C: out qsim_state_vector(2 downto 0)
);
end component;
begin
U1: paralell_process port map (CLK,OP_CODE,COUT,P0,P1,P2,P3,P4);
U2: unate_ctr port map (P0,P1,P2,P3,P4,P5,CLK,OP_CODE);
end behavior;
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- The unate_ctr Entity Description
ENTITY unate_ctr IS
port(
P0,P1,P2,P3,P4,P5,CLK: in qsim_state;
C: out qsim_state_vector (2 downto 0));
END unate_ctr ;
ARCHITECTURE behavior of unate_ctr IS
type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
signal CURRENT_STATE, NEXT_STATE:
STATE_TYPE;
begin
-- Process to hold synchronous elements
SYNCH: process
begin
wait until CLK'event and CLK = '1';
CURRENT_STATE <= NEXT_STATE;
end process;
-- Process to hold unate_machine's logic
UNATE_STATE: process(CURRENT_STATE,P0,P1,P2,P3,P4,P5,CLK)
begin
case CURRENT_STATE is
when S0 =>
if (P0='0') then
C <= "000";
NEXT_STATE <= S1;
end if;
when S1 =>
if ((P0='1') and (P1='0')) then
C <= "001";
NEXT_STATE <= S2;
end if;
when S2 =>
if ((P0='1') and (P1='1') and (P2='0') and (P3='1')) then
C <= "010";
NEXT_STATE <= S2;
elsif ((P0='1') and (P1='1') and (P2='1') and (P3='0')) then
C <= "011";
NEXT_STATE <=S3;
end if;
when S3 =>
if ((P0='1') and (P1='1') and (P2='0') and (P3='1')) then
C <= "010";
NEXT_STATE <= S2;
elsif (P4='1') then
C <= "100";
NEXT_STATE <=S4;
end if;
when S4 =>
if (P5='1') then
C <= "101";
NEXT_STATE <= S5;
end if;
when S5 =>
NEXT_STATE <= S5;
end case;
end process UNATE_STATE;
end behavior;
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
-- Process_Cell Entity Description
entity Process_Cell is
port(
DIN_RIGHT: in qsim_state_vector (15 downto 0);
DOUT_LEFT: out qsim_state_vector (15 downto 0);
P0, P1, P2, P3: out qsim_state;
PROCESS_NUM: in integer range 0 to 255;
CLK: in qsim_state;
OP_CODE: in qsim_state_vector (2 downto 0));
end Process_Cell;
-- Process_Cell Architecture Description
architecture rtl of Process_Cell is
USE WORK.Quine_McCluskey_def.ALL;
-- Declare the ram memory
signal RAM_SHIFT: ram_memory;
signal RAM_RESULT: ram_memory;
signal SHIFT_INDEX: integer range 0 to ram_adrs;
signal RESULT_INDEX: integer range 0 to ram_adrs;
begin
MAIN_Process: process(CLK, DIN_RIGHT, PROCESS_NUM)
variable pnum, num_of_ones: integer range 0 to 255;
variable ram_index_shift, ram_index_result: integer range 0 to 255;
variable temp_index_shift, count: integer range 0 to 255;
variable temp_in, temp_st: qsim_state_vector (15 downto 0);
variable temp_rs, temp_out: qsim_state_vector (15 downto 0);
variable switch_flag, chk_rls: qsim_state;
variable RAM_temp: ram_memory;
begin
if(CLK = '1') then
-- the process is responsed with clock cycle.
CASE OP_CODE IS
when "000" =>
-- Reset the process cell
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
for i in 0 to ram_adrs loop
RAM_SHIFT(i) <= "1111111111111111";
RAM_RESULT(i) <= "1111111111111111";
end loop;
P0 <= '1';
when "001" =>
-- Load the machine i.e. the memorys
pnum := PROCESS_NUM;
ram_index_shift := 0;
num_of_ones := 0;
temp_in := rom(ram_index_shift);
while(temp_in /= "1111111111111111") loop
temp_st := temp_in and "0101010101010101";
for i in 0 to 15 loop
if(temp_st(i) = '1') then
num_of_ones := num_of_ones + 1;
end if;
end loop;
if(num_of_ones = pnum) then
RAM_SHIFT(ram_index_shift) <= temp_in;
end if;
ram_index_shift := ram_index_shift + 1;
temp_in := rom(ram_index_shift);
end loop;
DOUT_LEFT <= RAM_SHIFT(0);
P1 <= '1';
when "010" =>
-- Starting the operations
temp_in := DIN_RIGHT;
ram_index_result := RESULT_INDEX;
switch_flag := '0';
count := 0;
if(temp_in /= "1111111111111111") then
temp_index_shift := 0;
temp_rs := RAM_SHIFT(temp_index_shift);
while(temp_rs /= "1111111111111111") loop
look_for_solution(temp_in, temp_rs, temp_out, chk_rls);
if(chk_rls = '1') then
switch_flag := '1';
count := count + 1;
RAM_temp(count) := temp_out;
end if;
temp_index_shift := temp_index_shift + 1;
temp_rs := RAM_SHIFT(temp_index_shift);
end loop;
if(switch_flag = '1') then
RAM_RESULT(ram_index_result) <= temp_in;
ram_index_result := ram_index_result + 1;
else
for i in 1 to count loop
RAM_RESULT(ram_index_result) <= temp_in;
ram_index_result := ram_index_result + 1;
end loop;
end if;
ram_index_shift := SHIFT_INDEX;
ram_index_shift := ram_index_shift + 1;
SHIFT_INDEX <= ram_index_shift;
RESULT_INDEX <= ram_index_result;
DOUT_LEFT <= RAM_SHIFT(ram_index_shift);
else
P2 <= '1';
P3 <= '0';
end if;
when "011" =>
-- Paraper for the next simplification
ram_index_result := 0;
temp_rs := RAM_RESULT(ram_index_result);
if(temp_rs /= "1111111111111111") then
while(temp_rs /= "1111111111111111") loop
RAM_SHIFT(ram_index_result) <= RAM_RESULT(ram_index_result);
RAM_RESULT(ram_index_result) <= "1111111111111111";
ram_index_result := ram_index_result + 1;
end loop;
P3 <= '1';
P2 <= '0';
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
DOUT_LEFT <= RAM_SHIFT(0);
else
ram_index_shift := SHIFT_INDEX;
for i in 0 to ram_index_shift loop
RAM_SHIFT(ram_index_shift) <= "1111111111111111";
end loop;
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
DOUT_LEFT <= RAM_SHIFT(0);
P3 <= '1';
P2 <= '0';
end if;
end CASE;
end if;
end process MAIN_Process;
end rtl;
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
USE WORK.ALL;
entity paralell_process is
port( CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0);
COUT: out qsim_state_vector(15 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end paralell_process;
architecture behavior of paralell_process is
USE WORK.Quine_McCluskey_def.ALL;
signal CONNECT: ram_memory;
signal P0: qsim_state_vector(7 downto 0):="00000000";
signal P1: qsim_state_vector(7 downto 0):="00000000";
signal P2: qsim_state_vector(7 downto 0):="00000000";
signal P3: qsim_state_vector(7 downto 0):="00000000";
signal P_END: qsim_state_vector(15 downto 0):="1111111111111111";
signal PNUM0: integer range 0 to 255 := 1;
signal PNUM1: integer range 0 to 255 := 2;
signal PNUM2: integer range 0 to 255 := 3;
signal PNUM3: integer range 0 to 255 := 4;
signal PNUM4: integer range 0 to 255 := 5;
signal PNUM5: integer range 0 to 255 := 6;
signal PNUM6: integer range 0 to 255 := 7;
signal PNUM7: integer range 0 to 255 := 8;
component process_cell
port(DIN_RIGHT: in qsim_state_vector(15 downto 0);
DOUT_LEFT: out qsim_state_vector(15 downto 0);
P0, P1, P2, P3: out qsim_state;
PROCESS_NUM: in integer range 0 to 255;
CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0)
);
end component;
component comb_signal
port(P0,P1,P2,P3: in qsim_state_vector(7 downto 0);
PP0,PP1,PP2,PP3,PP4: out qsim_state
);
end component;
begin
U0: process_cell port map (CONNECT(0), COUT, P0(0), P1(0),
P2(0), P3(0), PNUM0, CLK, OP_CODE);
U1: process_cell port map (CONNECT(1), CONNECT(0), P0(1),
P1(1), P2(1), P3(1), PNUM1, CLK, OP_CODE);
U2: process_cell port map (CONNECT(2), CONNECT(1), P0(2),
P1(2), P2(2), P3(2), PNUM2, CLK, OP_CODE);
U3: process_cell port map (CONNECT(3), CONNECT(2), P0(3),
P1(3), P2(3), P3(3), PNUM3, CLK, OP_CODE);
U4: process_cell port map (CONNECT(4), CONNECT(3), P0(4),
P1(4), P2(4), P3(4),PNUM4, CLK, OP_CODE);
U5: process_cell port map (CONNECT(5), CONNECT(4), P0(5),
P1(5), P2(5), P3(5), PNUM5, CLK, OP_CODE);
U6: process_cell port map (CONNECT(6), CONNECT(5), P0(6),
P1(6), P2(6), P3(6), PNUM6, CLK, OP_CODE);
U7: process_cell port map (P_END, CONNECT(6), P0(7),
P1(7), P2(7), P3(7), PNUM7, CLK, OP_CODE);
U8: comb_signal port map (P0,P1,P2,P3,PP0,PP1,PP2,PP3,PP4);
end behavior;
library mgc_portable;
use mgc_portable.qsim_logic.all;
entity comb_signal is
port(
P0,P1,P2,P3: in qsim_state_vector(7 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end comb_signal;
architecture behavior of comb_signal is
Signal count: integer range 0 to 255 := 8;
begin
SET_Process: process(P0, P1, P2, P3)
begin
if(P0 = "11111111") then
PP0 <= '1';
else
PP0 <= '0';
end if;
if(P1 = "11111111") then
PP1 <= '1';
end if;
if(P2 = "11111111") then
PP2 <= '1';
end if;
if(P3 = "11111111") then
PP3 <= '1';
count <= count - 1;
end if;
if(count = 0) then
PP4 <= '1';
end if;
end process SET_Process;
end behavior;
-- This is package for the Unate function machine
-- In this package, there are definitions of RAM and
-- other functions.
LIBRARY mgc_portable;
USE mgc_portable.qsim_logic.ALL;
PACKAGE Quine_McCluskey_def IS
-- Declare the RAM structure
subtype ram_word is qsim_state_vector (15 downto 0);
type ram_memory is array (255 downto 0) of ram_word;
-- Declare the ram_adrs as a constant
constant ram_adrs: integer := 25;
-- Declare the rom length, which is decided by your satisfiability function
constant rom_range: integer := 6;
-- Declare the tri_count carry out index, so that for small satisfiability
-- function (less than 8 variables) you do not need to go all the way to
-- 16 bits.
constant cy_index: integer := 3;
-- Declare a type for the purpose of array
type int_array is array (integer range 0 to 25) of integer;
-- Define a ROM to store the any given satisfiability function.
type rom_table is array (6 downto 0) of ram_word;
-- Define a procedure to resolve some of the iterms
PROCEDURE look_for_solution(DIN_A, DIN_B: in qsim_state_vector(15 downto 0);
DOUT: out qsim_state_vector(15 downto 0); chk_rls: out qsim_state);
-- Store the following Given Function in a given ROM.
-- The Satisfiability functoion is as follows:
-- F=SUM(4,20,21,36,52,53,54,55)
-- Also follow the convertion 01--negative, 10-positive, 00-donot care
constant rom: rom_table:=rom_table'(
"0000000010001010", -- ROM content
"0000000010101000",
"0000000000000101",
"0000000010010100",
"0000000001100100",
"1111111111111111",
"1111111111111111");
END Quine_McCluskey_def;
PACKAGE BODY Quine_McCluskey_def IS
PROCEDURE look_for_solution(DIN_A, DIN_B: in qsim_state_vector(15 downto 0);
DOUT: out qsim_state_vector(15 downto 0); chk_rls: out qsim_state) IS
variable eq_ident: qsim_state_vector(7 downto 0);
variable num_ones: integer:=0;
variable j: integer;
begin
for i in 1 to 8 loop
j:=i*2-1;
eq_ident(i-1):=((not DIN_A(j-1))and(not DIN_A(j))and(not DIN_B(j-1))and(not DIN_B(j)))
or((not DIN_A(j-1))and( DIN_A(j))and(not DIN_B(j-1))and( DIN_B(j)))
or(( DIN_A(j-1))and(not DIN_A(j))and( DIN_B(j-1))and(not DIN_B(j)));
eq_ident(i-1):=not(eq_ident(i-1));
if(eq_ident(i-1)='1') then
num_ones:=num_ones+1;
end if;
end loop;
if(num_ones=1) then
DOUT :=DIN_A and DIN_B;
chk_rls :='1';
else
DOUT :="1111111111111111";
chk_rls :='0';
end if;
end look_for_solution;
end Quine_McCluskey_def;
------------------------------------------------------------------
From zsida@ee.pdx.edu Fri Dec 9 11:13:03 1994
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Date: Fri, 9 Dec 94 11:13:02 PST
From: zsida@ee.pdx.edu
Message-Id: <9412091913.AA03282@flotsam.ee.pdx.edu>
To: mperkows@ee.pdx.edu
Status: R
Hi Dr. Perkowski:
This is partial codes of the Unate function project, The code
is try to implement the Quine_McCluskey methods in a parallel fashion
by define each process hold one term, The term is hold is such a
order that each process only differ in one positive literal. SO that
the process only need to get imformation from it right. but due to time
constrains, We have not be able to finish it, but all the code code here
compiled and partially simulated. if we have time, we will continune this
project.
Sida Zhou, Vaughn Zechmann, Zhiw Wang, Hongfei Wu.
------------------------------------------------------------------------
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
USE WORK.ALL;
entity unate_machine is
port( CLK: in qsim_state;
COUT: out qsim_state_vector(15 downto 0)
);
end unate_machine;
architecture behavior of unate_machine is
USE WORK.Quine_McCluskey_def.ALL;
signal P0,P1,P2,P3,P4,P5: qsim_state:='0';
signal OP_CODE: qsim_state_vector(2 downto 0):="000";
component paralell_process
port( CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0);
COUT: out qsim_state_vector(15 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end component;
component unate_ctr
port( P0,P1,P2,P3,P4,P5,CLK: in qsim_state;
C: out qsim_state_vector(2 downto 0)
);
end component;
begin
U1: paralell_process port map (CLK,OP_CODE,COUT,P0,P1,P2,P3,P4);
U2: unate_ctr port map (P0,P1,P2,P3,P4,P5,CLK,OP_CODE);
end behavior;
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- The unate_ctr Entity Description
ENTITY unate_ctr IS
port(
P0,P1,P2,P3,P4,P5,CLK: in qsim_state;
C: out qsim_state_vector (2 downto 0));
END unate_ctr ;
ARCHITECTURE behavior of unate_ctr IS
type STATE_TYPE is (S0,S1,S2,S3,S4,S5);
signal CURRENT_STATE, NEXT_STATE:
STATE_TYPE;
begin
-- Process to hold synchronous elements
SYNCH: process
begin
wait until CLK'event and CLK = '1';
CURRENT_STATE <= NEXT_STATE;
end process;
-- Process to hold unate_machine's logic
UNATE_STATE: process(CURRENT_STATE,P0,P1,P2,P3,P4,P5,CLK)
begin
case CURRENT_STATE is
when S0 =>
if (P0='0') then
C <= "000";
NEXT_STATE <= S1;
end if;
when S1 =>
if ((P0='1') and (P1='0')) then
C <= "001";
NEXT_STATE <= S2;
end if;
when S2 =>
if ((P0='1') and (P1='1') and (P2='0') and (P3='1')) then
C <= "010";
NEXT_STATE <= S2;
elsif ((P0='1') and (P1='1') and (P2='1') and (P3='0')) then
C <= "011";
NEXT_STATE <=S3;
end if;
when S3 =>
if ((P0='1') and (P1='1') and (P2='0') and (P3='1')) then
C <= "010";
NEXT_STATE <= S2;
elsif (P4='1') then
C <= "100";
NEXT_STATE <=S4;
end if;
when S4 =>
if (P5='1') then
C <= "101";
NEXT_STATE <= S5;
end if;
when S5 =>
NEXT_STATE <= S5;
end case;
end process UNATE_STATE;
end behavior;
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
-- Process_Cell Entity Description
entity Process_Cell is
port(
DIN_RIGHT: in qsim_state_vector (15 downto 0);
DOUT_LEFT: out qsim_state_vector (15 downto 0);
P0, P1, P2, P3: out qsim_state;
PROCESS_NUM: in integer range 0 to 255;
CLK: in qsim_state;
OP_CODE: in qsim_state_vector (2 downto 0));
end Process_Cell;
-- Process_Cell Architecture Description
architecture rtl of Process_Cell is
USE WORK.Quine_McCluskey_def.ALL;
-- Declare the ram memory
signal RAM_SHIFT: ram_memory;
signal RAM_RESULT: ram_memory;
signal SHIFT_INDEX: integer range 0 to ram_adrs;
signal RESULT_INDEX: integer range 0 to ram_adrs;
begin
MAIN_Process: process(CLK, DIN_RIGHT, PROCESS_NUM)
variable pnum, num_of_ones: integer range 0 to 255;
variable ram_index_shift, ram_index_result: integer range 0 to 255;
variable temp_index_shift, count: integer range 0 to 255;
variable temp_in, temp_st: qsim_state_vector (15 downto 0);
variable temp_rs, temp_out: qsim_state_vector (15 downto 0);
variable switch_flag, chk_rls: qsim_state;
variable RAM_temp: ram_memory;
begin
if(CLK = '1') then
-- the process is responsed with clock cycle.
CASE OP_CODE IS
when "000" =>
-- Reset the process cell
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
for i in 0 to ram_adrs loop
RAM_SHIFT(i) <= "1111111111111111";
RAM_RESULT(i) <= "1111111111111111";
end loop;
P0 <= '1';
when "001" =>
-- Load the machine i.e. the memorys
pnum := PROCESS_NUM;
ram_index_shift := 0;
num_of_ones := 0;
temp_in := rom(ram_index_shift);
while(temp_in /= "1111111111111111") loop
temp_st := temp_in and "0101010101010101";
for i in 0 to 15 loop
if(temp_st(i) = '1') then
num_of_ones := num_of_ones + 1;
end if;
end loop;
if(num_of_ones = pnum) then
RAM_SHIFT(ram_index_shift) <= temp_in;
end if;
ram_index_shift := ram_index_shift + 1;
temp_in := rom(ram_index_shift);
end loop;
DOUT_LEFT <= RAM_SHIFT(0);
P1 <= '1';
when "010" =>
-- Starting the operations
temp_in := DIN_RIGHT;
ram_index_result := RESULT_INDEX;
switch_flag := '0';
count := 0;
if(temp_in /= "1111111111111111") then
temp_index_shift := 0;
temp_rs := RAM_SHIFT(temp_index_shift);
while(temp_rs /= "1111111111111111") loop
look_for_solution(temp_in, temp_rs, temp_out, chk_rls);
if(chk_rls = '1') then
switch_flag := '1';
count := count + 1;
RAM_temp(count) := temp_out;
end if;
temp_index_shift := temp_index_shift + 1;
temp_rs := RAM_SHIFT(temp_index_shift);
end loop;
if(switch_flag = '1') then
RAM_RESULT(ram_index_result) <= temp_in;
ram_index_result := ram_index_result + 1;
else
for i in 1 to count loop
RAM_RESULT(ram_index_result) <= temp_in;
ram_index_result := ram_index_result + 1;
end loop;
end if;
ram_index_shift := SHIFT_INDEX;
ram_index_shift := ram_index_shift + 1;
SHIFT_INDEX <= ram_index_shift;
RESULT_INDEX <= ram_index_result;
DOUT_LEFT <= RAM_SHIFT(ram_index_shift);
else
P2 <= '1';
P3 <= '0';
end if;
when "011" =>
-- Paraper for the next simplification
ram_index_result := 0;
temp_rs := RAM_RESULT(ram_index_result);
if(temp_rs /= "1111111111111111") then
while(temp_rs /= "1111111111111111") loop
RAM_SHIFT(ram_index_result) <= RAM_RESULT(ram_index_result);
RAM_RESULT(ram_index_result) <= "1111111111111111";
ram_index_result := ram_index_result + 1;
end loop;
P3 <= '1';
P2 <= '0';
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
DOUT_LEFT <= RAM_SHIFT(0);
else
ram_index_shift := SHIFT_INDEX;
for i in 0 to ram_index_shift loop
RAM_SHIFT(ram_index_shift) <= "1111111111111111";
end loop;
SHIFT_INDEX <= 0;
RESULT_INDEX <= 0;
DOUT_LEFT <= RAM_SHIFT(0);
P3 <= '1';
P2 <= '0';
end if;
end CASE;
end if;
end process MAIN_Process;
end rtl;
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
USE WORK.ALL;
entity paralell_process is
port( CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0);
COUT: out qsim_state_vector(15 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end paralell_process;
architecture behavior of paralell_process is
USE WORK.Quine_McCluskey_def.ALL;
signal CONNECT: ram_memory;
signal P0: qsim_state_vector(7 downto 0):="00000000";
signal P1: qsim_state_vector(7 downto 0):="00000000";
signal P2: qsim_state_vector(7 downto 0):="00000000";
signal P3: qsim_state_vector(7 downto 0):="00000000";
signal P_END: qsim_state_vector(15 downto 0):="1111111111111111";
signal PNUM0: integer range 0 to 255 := 1;
signal PNUM1: integer range 0 to 255 := 2;
signal PNUM2: integer range 0 to 255 := 3;
signal PNUM3: integer range 0 to 255 := 4;
signal PNUM4: integer range 0 to 255 := 5;
signal PNUM5: integer range 0 to 255 := 6;
signal PNUM6: integer range 0 to 255 := 7;
signal PNUM7: integer range 0 to 255 := 8;
component process_cell
port(DIN_RIGHT: in qsim_state_vector(15 downto 0);
DOUT_LEFT: out qsim_state_vector(15 downto 0);
P0, P1, P2, P3: out qsim_state;
PROCESS_NUM: in integer range 0 to 255;
CLK: in qsim_state;
OP_CODE: in qsim_state_vector(2 downto 0)
);
end component;
component comb_signal
port(P0,P1,P2,P3: in qsim_state_vector(7 downto 0);
PP0,PP1,PP2,PP3,PP4: out qsim_state
);
end component;
begin
U0: process_cell port map (CONNECT(0), COUT, P0(0), P1(0),
P2(0), P3(0), PNUM0, CLK, OP_CODE);
U1: process_cell port map (CONNECT(1), CONNECT(0), P0(1),
P1(1), P2(1), P3(1), PNUM1, CLK, OP_CODE);
U2: process_cell port map (CONNECT(2), CONNECT(1), P0(2),
P1(2), P2(2), P3(2), PNUM2, CLK, OP_CODE);
U3: process_cell port map (CONNECT(3), CONNECT(2), P0(3),
P1(3), P2(3), P3(3), PNUM3, CLK, OP_CODE);
U4: process_cell port map (CONNECT(4), CONNECT(3), P0(4),
P1(4), P2(4), P3(4),PNUM4, CLK, OP_CODE);
U5: process_cell port map (CONNECT(5), CONNECT(4), P0(5),
P1(5), P2(5), P3(5), PNUM5, CLK, OP_CODE);
U6: process_cell port map (CONNECT(6), CONNECT(5), P0(6),
P1(6), P2(6), P3(6), PNUM6, CLK, OP_CODE);
U7: process_cell port map (P_END, CONNECT(6), P0(7),
P1(7), P2(7), P3(7), PNUM7, CLK, OP_CODE);
U8: comb_signal port map (P0,P1,P2,P3,PP0,PP1,PP2,PP3,PP4);
end behavior;
library mgc_portable;
use mgc_portable.qsim_logic.all;
entity comb_signal is
port(
P0,P1,P2,P3: in qsim_state_vector(7 downto 0);
PP0, PP1, PP2, PP3, PP4: out qsim_state
);
end comb_signal;
architecture behavior of comb_signal is
Signal count: integer range 0 to 255 := 8;
begin
SET_Process: process(P0, P1, P2, P3)
begin
if(P0 = "11111111") then
PP0 <= '1';
else
PP0 <= '0';
end if;
if(P1 = "11111111") then
PP1 <= '1';
end if;
if(P2 = "11111111") then
PP2 <= '1';
end if;
if(P3 = "11111111") then
PP3 <= '1';
count <= count - 1;
end if;
if(count = 0) then
PP4 <= '1';
end if;
end process SET_Process;
end behavior;
-- This is package for the Unate function machine
-- In this package, there are definitions of RAM and
-- other functions.
LIBRARY mgc_portable;
USE mgc_portable.qsim_logic.ALL;
PACKAGE Quine_McCluskey_def IS
-- Declare the RAM structure
subtype ram_word is qsim_state_vector (15 downto 0);
type ram_memory is array (255 downto 0) of ram_word;
-- Declare the ram_adrs as a constant
constant ram_adrs: integer := 25;
-- Declare the rom length, which is decided by your satisfiability function
constant rom_range: integer := 6;
-- Declare the tri_count carry out index, so that for small satisfiability
-- function (less than 8 variables) you do not need to go all the way to
-- 16 bits.
constant cy_index: integer := 3;
-- Declare a type for the purpose of array
type int_array is array (integer range 0 to 25) of integer;
-- Define a ROM to store the any given satisfiability function.
type rom_table is array (6 downto 0) of ram_word;
-- Define a procedure to resolve some of the iterms
PROCEDURE look_for_solution(DIN_A, DIN_B: in qsim_state_vector(15 downto 0);
DOUT: out qsim_state_vector(15 downto 0); chk_rls: out qsim_state);
-- Store the following Given Function in a given ROM.
-- The Satisfiability functoion is as follows:
-- F=SUM(4,20,21,36,52,53,54,55)
-- Also follow the convertion 01--negative, 10-positive, 00-donot care
constant rom: rom_table:=rom_table'(
"0000000010001010", -- ROM content
"0000000010101000",
"0000000000000101",
"0000000010010100",
"0000000001100100",
"1111111111111111",
"1111111111111111");
END Quine_McCluskey_def;
PACKAGE BODY Quine_McCluskey_def IS
PROCEDURE look_for_solution(DIN_A, DIN_B: in qsim_state_vector(15 downto 0);
DOUT: out qsim_state_vector(15 downto 0); chk_rls: out qsim_state) IS
variable eq_ident: qsim_state_vector(7 downto 0);
variable num_ones: integer:=0;
variable j: integer;
begin
for i in 1 to 8 loop
j:=i*2-1;
eq_ident(i-1):=((not DIN_A(j-1))and(not DIN_A(j))and(not DIN_B(j-1))and(not DIN_B(j)))
or((not DIN_A(j-1))and( DIN_A(j))and(not DIN_B(j-1))and( DIN_B(j)))
or(( DIN_A(j-1))and(not DIN_A(j))and( DIN_B(j-1))and(not DIN_B(j)));
eq_ident(i-1):=not(eq_ident(i-1));
if(eq_ident(i-1)='1') then
num_ones:=num_ones+1;
end if;
end loop;
if(num_ones=1) then
DOUT :=DIN_A and DIN_B;
chk_rls :='1';
else
DOUT :="1111111111111111";
chk_rls :='0';
end if;
end look_for_solution;
end Quine_McCluskey_def;
==================================