CAT policies.
From Zsida Zhou.
Organization PSU
Date 1995
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Description of this programm
-- This is a program to solve greatest common deviser
-- of any given two integers.
-----------------------------------------------------------
-- Signal Description
-- In the main programm following signal is used
-- 1) X, Y input of any two integer < 255.
-- 2) Z the output signal of the program.
-- 3) CLK the Clock.
-- 4) PP1, PP2 Output of the comparator.
-- 5) CC1, CC2, CC3 are control signal to control
-- the flow of this program.
-- 6) SUBB is a signal to control the adder to adder or
-- subtract, in this program is '1', which mean subtract.
-- Component Description
-- There are four components in this program.
-- 1) Controller: which is the control units of this program.
-- 2) comparator: to comparator to numbers.
-- 3) AU, AU1: are adder/subtractors.
-- 4) Buffer_trans: Put the final results to Z.
-- Deviser Entity Description
entity Deviser is
port(
X,Y: buffer qsim_state_vector(7 downto 0);
CLK: in qsim_state;
Z: out qsim_state_vector(7 downto 0)
);
end Deviser;
-- Deviser Architecture Description
architecture Adv of Deviser is
signal PP1,PP2, CC1, CC2, CC3: qsim_state;
signal CCOUT1, CCOUT2: qsim_state;
signal DD1,DD2: qsim_state_vector(7 downto 0);
signal SUBB: qsim_state:='1';
component Controller
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end component;
component AU
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component AU1
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component comparator
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end component;
component Buf_trans
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3,CLK: in qsim_state
);
end component;
begin
U1: comparator port map (X,Y,PP1);
U2: comparator port map (Y,X,PP2);
U3: Controller port map (PP1,PP2,CLK,CC1,CC2,CC3);
U4: AU port map (X,Y,SUBB,CC1,CLK,CCOUT1);
U5: AU1 port map (X,Y,SUBB,CC2,CLK,CCOUT2);
U6: Buf_trans port map (X,Z,CC3,CLK);
end Adv;
-----------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Controller Entity Description
entity Controller is
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end Controller;
-- Controller Architecture Description
-- The Controller realize the following relations:
-- Q'=P1BARP2BAR + Q
-- C3=QBARP1BARP2BAR
-- C2=QBARP1BARP2
-- C1=QBARP1
architecture ctl of Controller is
signal pre_C1, pre_C2, pre_C3: qsim_state:='0';
signal QQ, DD: qsim_state:='0';
signal QQBAR: qsim_state:='1';
component Flip_Flop
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end component;
begin
Controller_Process: process(P1, P2, QQ, CLK)
begin
DD <= (QQ or ((not P1) and (not P2)));
pre_C3 <= ((not QQ) and ((not P1) and (not P2)));
pre_C2 <= ((not P1) and P2 and (not QQ));
pre_C1 <= (P1 and (not QQ));
end process Controller_Process;
U1: Flip_Flop port map(DD,CLK,QQ,QQBAR);
-- Assign outputs
C1 <= pre_C1;
C2 <= pre_C2;
C3 <= pre_C3;
end ctl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU Entity Description
entity AU is
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU;
-- AU Architecture Description
architecture rtl of AU is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & A;
if (SUB = '1') then
b_ext := '0' & not B;
else
b_ext := '0' & B;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_A: BLOCK(not CLK'STABLE and CLK = '0')
begin
A <= guarded A when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_A;
-- Assign flags
COUT <= pre_D(8);
end rtl;
-------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU1 Entity Description
entity AU1 is
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU1;
-- AU1 Architecture Description
architecture rtl of AU1 is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & B;
if (SUB = '1') then
b_ext := '0' & not A;
else
b_ext := '0' & A;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_B: BLOCK(not CLK'STABLE and CLK = '0')
begin
B <= guarded B when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_B;
-- Assign flags
COUT <= pre_D(8);
end rtl;
--------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- comparator Entity Description
entity comparator is
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end comparator;
-- comparator Architecture Description
architecture rtl of comparator is
begin
COMPARATOR_process: process(A,B)
begin
-- A > B
gt <= (A > B);
end process COMPARATOR_process;
end rtl;
---------------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Buf Entity Description
entity Buf_trans is
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3, CLK: in qsim_state
);
end Buf_trans;
-- Buf_trans Architecture Description
architecture btl of Buf_trans is
begin
BUF_C: BLOCK(C3 = '1')
begin
Q1_OUT <= guarded A1 when C3 ='1' else "XXXXXXXX";
end BLOCK BUF_C;
end btl;
---------------------
ANOTERH VERSION
From zsida@ee.pdx.edu Fri Nov 18 00:25:31 1994
GREATEST COMMON DIVISOR.
--------------------------
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Description of this programm
-- This is a program to solve greatest common deviser
-- of any given two integers. This is a different realization.
-----------------------------------------------------------
-- Signal Description
-- In the main programm following signal is used
-- 1) X, Y input of any two integer < 255.
-- 2) Z the output signal of the program.
-- 3) CLK the Clock.
-- 4) PP1, PP2 Output of the comparator.
-- 5) CC1, CC2, CC3, CC4, CC5, CC6 are control signal to
-- control the flow of this program.
-- 6) SUBB is a signal to control the adder to adder or
-- subtract, in this program is '1', which mean subtract.
-- 7) U is intermediate signal.
-- Component Description
-- There are four components in this program.
-- 1) Controller: which is the control units of this program.
-- 2) comparator: to comparator to numbers.
-- 3) AU3: are adder/subtractors.
-- 4) rgst: It is the shift register.
-- 5) rgst1: It is mux, to resolve the signals.
-- Alt_Deviser Entity Description
entity Alt_Deviser is
port(
X,Y: buffer qsim_state_vector(7 downto 0);
CLK: in qsim_state;
Z: buffer qsim_state_vector(7 downto 0)
);
end Alt_Deviser;
-- Alt_Deviser Architecture Description
architecture Adv of Alt_Deviser is
signal PP1,PP2, CC1, CC2, CC3: qsim_state;
signal CC4, CC5, CC6, CCOUT1: qsim_state;
signal U,DD1,DD2: qsim_state_vector(7 downto 0);
signal SUBB: qsim_state:='1';
component alt_ctr
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3,C4,C5,C6: out qsim_state
);
end component;
component AU3
port(
A, B: in qsim_state_vector(7 downto 0);
D: buffer qsim_state_vector(7 downto 0);
SUB, ENB1,ENB2, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component comparator
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end component;
component rgst
port(
DIN_OUT: buffer qsim_state_vector(7 downto 0);
D_IN: in qsim_state_vector(7 downto 0);
C: in qsim_state
);
end component;
component rgst1
port(
DIN_OUT: buffer qsim_state_vector(7 downto 0);
D_IN,D_IN2: in qsim_state_vector(7 downto 0);
C1, C2: qsim_state
);
end component;
begin
U1: comparator port map (X,Y,PP1);
U2: comparator port map (Y,X,PP2);
U3: alt_ctr port map (PP1,PP2,CLK,CC1,CC2,CC3,CC4,CC5,CC6);
U4: AU3 port map (X,Y,DD1,SUBB,CC1,CC5,CLK,CCOUT1);
U5: rgst port map (U,Y,CC2);
U6: rgst port map (Y,X,CC3);
U7: rgst port map (DD2,U,CC4);
U8: rgst port map (Z,X,CC6);
U9: rgst1 port map (X,DD1,DD2,CC1,CC4);
end Adv;
----------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Alt_Ctr Entity Description
entity alt_ctr is
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3,C4,C5,C6: out qsim_state
);
end alt_ctr;
-- Atl_Ctr Architecture Description
-- The Controller realize the following relations:
-- Q1'=Q2BARQ3BAR(Q1+P1BARP2BAR)
-- Q2'=Q1BARQQ3
-- Q3'=Q1BARQ2BAR(Q3+P1BARP2)
-- C6 =Q1BARQ2BARQ3BARP1BARP2BAR
-- C5 =Q1BARQ2Q3BAR
-- C4 =Q1BARQ2Q3
-- C3 =Q1BARQ2BARQ3
-- C2 =Q1BARQ2BARQ3BARP1BARP2
-- C1 =Q1BARQ2BARQ3BARP1
architecture ctl of alt_ctr is
signal pre_C1, pre_C2, pre_C3: qsim_state:='0';
signal pre_C4, pre_C5, pre_C6: qsim_state:='0';
signal QQ1, DD1: qsim_state:='0';
signal QQ2, DD2: qsim_state:='0';
signal QQ3, DD3: qsim_state:='0';
signal QQBAR1, QQBAR2, QQBAR3: qsim_state:='1';
component Flip_Flop
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end component;
begin
Controller_Process: process(P1,P2,QQ1,QQ2,QQ3)
begin
DD1 <= (((not QQ2) and (not QQ3)) and (QQ1 or ((not P1) and (not P2))));
DD2 <= ((not QQ1) and QQ3);
DD3 <= (((not QQ1) and (not QQ2)) and (QQ3 or ((not P1) and P2)));
pre_C6 <= ((not QQ1) and (not QQ2) and (not QQ3) and (not P1) and (not P2));
pre_C5 <= ((not QQ1) and QQ2 and (not QQ3));
pre_C4 <= ((not QQ1) and QQ2 and QQ3);
pre_C3 <= ((not QQ1) and (not QQ2) and QQ3);
pre_C2 <= ((not QQ1) and (not QQ2) and (not QQ3) and (not P1) and P2);
pre_C1 <= ((not QQ1) and (not QQ2) and (not QQ3) and P1);
end process Controller_Process;
U1: Flip_Flop port map(DD1,CLK,QQ1,QQBAR1);
U2: Flip_Flop port map(DD2,CLK,QQ2,QQBAR2);
U3: Flip_Flop port map(DD3,CLK,QQ3,QQBAR3);
-- Assign outputs
C1 <= pre_C1;
C2 <= pre_C2;
C3 <= pre_C3;
C4 <= pre_C4;
C5 <= pre_C5;
C6 <= pre_C6;
end ctl;
-------------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU3 Entity Description
entity AU3 is
port(
A,B: in qsim_state_vector(7 downto 0);
D: buffer qsim_state_vector(7 downto 0);
SUB, ENB1,ENB2, CLK: in qsim_state;
COUT: out qsim_state
);
end AU3;
-- AU3 Architecture Description
architecture rtl of AU3 is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB1,ENB2,A,B,D)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and ((ENB1='1') or (ENB2='1'))) then
-- zero extend inputs to include carry bit
a_ext := '0' & A;
if (SUB = '1') then
b_ext := '0' & not B;
else
b_ext := '0' & B;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
-- Assign flags
D <= pre_D (7 downto 0);
COUT <= pre_D(8);
end rtl;
---------------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- comparator Entity Description
entity comparator is
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end comparator;
-- comparator Architecture Description
architecture rtl of comparator is
begin
COMPARATOR_process: process(A,B)
begin
-- A > B
gt <= (A > B);
end process COMPARATOR_process;
end rtl;
----------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- rgst Entity Description
entity rgst is
port(
DIN_OUT: buffer qsim_state_vector(7 downto 0);
D_IN: in qsim_state_vector(7 downto 0);
C: in qsim_state
);
end rgst;
-- regiter Architecture Description
architecture BEHAVIOR of rgst is
begin
REG_BLOCK: BLOCK(C='1')
begin
DIN_OUT <= guarded DIN_OUT when C='0' else D_IN;
end BLOCK REG_BLOCK;
end BEHAVIOR;
------------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- rgst1 Entity Description
entity rgst1 is
port(
DIN_OUT: buffer qsim_state_vector(7 downto 0);
D_IN, D_IN2: in qsim_state_vector(7 downto 0);
C1, C2, C3: qsim_state
);
end rgst1;
-- regiter Architecture Description
architecture BEHAVIOR of rgst1 is
begin
STORE_REGISTER_Process: process
begin
wait on D_IN, D_IN2;
if(C2 = '1') then
DIN_OUT <= D_IN2;
elsif ((C1 = '1') or (C3 = '1')) then
DIN_OUT <=D_IN;
end if;
end process STORE_REGISTER_Process;
end BEHAVIOR;
********************************************8
From zsida@ee.pdx.edu Fri Nov 18 00:25:40 1994
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From: zsida@ee.pdx.edu
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To: mperkows@ee.pdx.edu
Status: RO
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Description of this programm
-- This is a program to solve smallest common multipler
-- of any given two integers.
-----------------------------------------------------------
-- Signal Description
-- In the main programm following signal is used
-- 1) X, Y input of any two integer < 255.
-- 2) Z the output signal of the program.
-- 3) CLK the Clock.
-- 4) PP1, PP2 Output of the comparator.
-- 5) CC1, CC2, CC3 are control signal to control
-- the flow of this program.
-- 6) SUBB is a signal to control the adder to adder or
-- subtract, in this program is '0', which mean subtract.
-- Component Description
-- There are four components in this program.
-- 1) Controller: which is the control units of this program.
-- 2) comparator: to comparator to numbers.
-- 3) AU, AU1: are adder/subtractors.
-- 4) Buffer_trans: Put the final results to Z.
-- 5) INIT: is a register to store the initial value of X,Y.
-- GMultipler Entity Description
entity GMultipler is
port(
X,Y: buffer qsim_state_vector(7 downto 0);
CLK: in qsim_state;
Z: out qsim_state_vector(7 downto 0)
);
end GMultipler;
-- GMultipler Architecture Description
architecture Adv of GMultipler is
signal X0,Y0: qsim_state_vector(7 downto 0):="00000000";
signal PP1,PP2, CC1, CC2, CC3: qsim_state;
signal CCOUT1, CCOUT2: qsim_state;
signal DD1,DD2: qsim_state_vector(7 downto 0);
signal SUBB: qsim_state:='0';
signal first_time: qsim_state:= '1';
component Controller
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end component;
component AU
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component AU1
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component comparator
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end component;
component Buf_trans
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3,CLK: in qsim_state
);
end component;
component INIT
port(
A,B: in qsim_state_vector(7 downto 0);
A0,B0: buffer qsim_state_vector(7 downto 0);
first_time: buffer qsim_state
);
end component;
begin
U1: comparator port map (Y,X,PP1);
U2: comparator port map (X,Y,PP2);
U3: Controller port map (PP1,PP2,CLK,CC1,CC2,CC3);
U4: AU port map (X,X0,SUBB,CC1,CLK,CCOUT1);
U5: AU1 port map (Y0,Y,SUBB,CC2,CLK,CCOUT2);
U6: Buf_trans port map (X,Z,CC3,CLK);
U7: INIT port map (X,Y,X0,Y0,first_time);
end Adv;
-----------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Controller Entity Description
entity Controller is
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end Controller;
-- Controller Architecture Description
-- The Controller realize the following relations:
-- Q'=P1BARP2BAR + Q
-- C3=QBARP1BARP2BAR
-- C2=QBARP1BARP2
-- C1=QBARP1
architecture ctl of Controller is
signal pre_C1, pre_C2, pre_C3: qsim_state:='0';
signal QQ, DD: qsim_state:='0';
signal QQBAR: qsim_state:='1';
component Flip_Flop
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end component;
begin
Controller_Process: process(P1, P2, QQ, CLK)
begin
DD <= (QQ or ((not P1) and (not P2)));
pre_C3 <= ((not QQ) and ((not P1) and (not P2)));
pre_C2 <= ((not P1) and P2 and (not QQ));
pre_C1 <= (P1 and (not QQ));
end process Controller_Process;
U1: Flip_Flop port map(DD,CLK,QQ,QQBAR);
-- Assign outputs
C1 <= pre_C1;
C2 <= pre_C2;
C3 <= pre_C3;
end ctl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU Entity Description
entity AU is
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU;
-- AU Architecture Description
architecture rtl of AU is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & A;
if (SUB = '1') then
b_ext := '0' & not B;
else
b_ext := '0' & B;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_A: BLOCK(not CLK'STABLE and CLK = '0')
begin
A <= guarded A when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_A;
-- Assign flags
COUT <= pre_D(8);
end rtl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU1 Entity Description
entity AU1 is
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU1;
-- AU1 Architecture Description
architecture rtl of AU1 is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & B;
if (SUB = '1') then
b_ext := '0' & not A;
else
b_ext := '0' & A;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_B: BLOCK(not CLK'STABLE and CLK = '0')
begin
B <= guarded B when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_B;
-- Assign flags
COUT <= pre_D(8);
end rtl;
--------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- comparator Entity Description
entity comparator is
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end comparator;
-- comparator Architecture Description
architecture rtl of comparator is
begin
COMPARATOR_process: process(A,B)
begin
-- A > B
gt <= (A > B);
end process COMPARATOR_process;
end rtl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Buf Entity Description
entity Buf_trans is
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3, CLK: in qsim_state
);
end Buf_trans;
-- Buf_trans Architecture Description
architecture btl of Buf_trans is
begin
BUF_C: BLOCK(C3 = '1')
begin
Q1_OUT <= guarded A1 when C3 ='1' else "XXXXXXXX";
end BLOCK BUF_C;
end btl;
--------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- INIT Entity Description
entity INIT is
port(
A,B: in qsim_state_vector(7 downto 0);
A0,B0: buffer qsim_state_vector(7 downto 0):="00000000";
first_time: buffer qsim_state:='1'
);
end INIT;
-- INIT Architecture Description
architecture rtl of INIT is
begin
INI_process: process
begin
wait for 15ns;
if(first_time = '1') then
A0 <= A;
B0 <= B;
first_time <= '0';
end if;
end process INI_process;
end rtl;
********************************
From zsida@ee.pdx.edu Fri Nov 18 00:25:40 1994
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Date: Fri, 18 Nov 94 00:25:38 PST
From: zsida@ee.pdx.edu
Message-Id: <9411180825.AA23354@flotsam.ee.pdx.edu>
To: mperkows@ee.pdx.edu
Status: RO
library mgc_portable, WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Description of this programm
-- This is a program to solve smallest common multipler
-- of any given two integers.
-----------------------------------------------------------
-- Signal Description
-- In the main programm following signal is used
-- 1) X, Y input of any two integer < 255.
-- 2) Z the output signal of the program.
-- 3) CLK the Clock.
-- 4) PP1, PP2 Output of the comparator.
-- 5) CC1, CC2, CC3 are control signal to control
-- the flow of this program.
-- 6) SUBB is a signal to control the adder to adder or
-- subtract, in this program is '0', which mean subtract.
-- Component Description
-- There are four components in this program.
-- 1) Controller: which is the control units of this program.
-- 2) comparator: to comparator to numbers.
-- 3) AU, AU1: are adder/subtractors.
-- 4) Buffer_trans: Put the final results to Z.
-- 5) INIT: is a register to store the initial value of X,Y.
-- GMultipler Entity Description
entity GMultipler is
port(
X,Y: buffer qsim_state_vector(7 downto 0);
CLK: in qsim_state;
Z: out qsim_state_vector(7 downto 0)
);
end GMultipler;
-- GMultipler Architecture Description
architecture Adv of GMultipler is
signal X0,Y0: qsim_state_vector(7 downto 0):="00000000";
signal PP1,PP2, CC1, CC2, CC3: qsim_state;
signal CCOUT1, CCOUT2: qsim_state;
signal DD1,DD2: qsim_state_vector(7 downto 0);
signal SUBB: qsim_state:='0';
signal first_time: qsim_state:= '1';
component Controller
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end component;
component AU
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component AU1
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end component;
component comparator
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end component;
component Buf_trans
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3,CLK: in qsim_state
);
end component;
component INIT
port(
A,B: in qsim_state_vector(7 downto 0);
A0,B0: buffer qsim_state_vector(7 downto 0);
first_time: buffer qsim_state
);
end component;
begin
U1: comparator port map (Y,X,PP1);
U2: comparator port map (X,Y,PP2);
U3: Controller port map (PP1,PP2,CLK,CC1,CC2,CC3);
U4: AU port map (X,X0,SUBB,CC1,CLK,CCOUT1);
U5: AU1 port map (Y0,Y,SUBB,CC2,CLK,CCOUT2);
U6: Buf_trans port map (X,Z,CC3,CLK);
U7: INIT port map (X,Y,X0,Y0,first_time);
end Adv;
-----------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Controller Entity Description
entity Controller is
port(
P1,P2,CLK: in qsim_state;
C1,C2,C3: out qsim_state
);
end Controller;
-- Controller Architecture Description
-- The Controller realize the following relations:
-- Q'=P1BARP2BAR + Q
-- C3=QBARP1BARP2BAR
-- C2=QBARP1BARP2
-- C1=QBARP1
architecture ctl of Controller is
signal pre_C1, pre_C2, pre_C3: qsim_state:='0';
signal QQ, DD: qsim_state:='0';
signal QQBAR: qsim_state:='1';
component Flip_Flop
port(
D,CLK: in qsim_state;
Q,QBAR: out qsim_state
);
end component;
begin
Controller_Process: process(P1, P2, QQ, CLK)
begin
DD <= (QQ or ((not P1) and (not P2)));
pre_C3 <= ((not QQ) and ((not P1) and (not P2)));
pre_C2 <= ((not P1) and P2 and (not QQ));
pre_C1 <= (P1 and (not QQ));
end process Controller_Process;
U1: Flip_Flop port map(DD,CLK,QQ,QQBAR);
-- Assign outputs
C1 <= pre_C1;
C2 <= pre_C2;
C3 <= pre_C3;
end ctl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU Entity Description
entity AU is
port(
A: buffer qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU;
-- AU Architecture Description
architecture rtl of AU is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & A;
if (SUB = '1') then
b_ext := '0' & not B;
else
b_ext := '0' & B;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_A: BLOCK(not CLK'STABLE and CLK = '0')
begin
A <= guarded A when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_A;
-- Assign flags
COUT <= pre_D(8);
end rtl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- AU1 Entity Description
entity AU1 is
port(
A: in qsim_state_vector(7 downto 0);
B: buffer qsim_state_vector(7 downto 0);
SUB, ENB, CLK: in qsim_state;
COUT: out qsim_state
);
end AU1;
-- AU1 Architecture Description
architecture rtl of AU1 is
signal pre_D : qsim_state_vector(8 downto 0);
signal pre_OV : qsim_state;
begin
ARITHMETIC_Process: process(CLK,ENB,A,B)
variable fct_out : qsim_state_vector(8 downto 0);
variable a_ext,b_ext : qsim_state_vector(8 downto 0);
variable carry_ext : qsim_state_vector(1 downto 0);
variable msb : integer;
begin
if (CLK'event and (CLK = '1') and (ENB='1')) then
-- zero extend inputs to include carry bit
a_ext := '0' & B;
if (SUB = '1') then
b_ext := '0' & not A;
else
b_ext := '0' & A;
end if;
carry_ext := (OTHERS => '0');
carry_ext(0) := SUB;
-- ADDSUB
fct_out := a_ext + b_ext + carry_ext;
-- Assign to signal for use outside process
pre_D <= fct_out;
-- Calculate overflow bit
if (a_ext(7) = b_ext(7) and fct_out(7) = not a_ext(7)) then
pre_OV <= '1';
else
pre_OV <= '0';
end if;
end if;
end process ARITHMETIC_Process;
BUF_B: BLOCK(not CLK'STABLE and CLK = '0')
begin
B <= guarded B when ENB ='0' else pre_D(7 downto 0) ;
end BLOCK BUF_B;
-- Assign flags
COUT <= pre_D(8);
end rtl;
--------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- comparator Entity Description
entity comparator is
port(
A: in qsim_state_vector(7 downto 0);
B: in qsim_state_vector(7 downto 0);
GT: out qsim_state
);
end comparator;
-- comparator Architecture Description
architecture rtl of comparator is
begin
COMPARATOR_process: process(A,B)
begin
-- A > B
gt <= (A > B);
end process COMPARATOR_process;
end rtl;
---------------------------------------------------------------------
library mgc_portable,WORK;
use mgc_portable.qsim_logic.all;
use WORK.all;
-- Buf Entity Description
entity Buf_trans is
port(
A1: in qsim_state_vector(7 downto 0);
Q1_OUT: out qsim_state_vector(7 downto 0);
C3, CLK: in qsim_state
);
end Buf_trans;
-- Buf_trans Architecture Description
architecture btl of Buf_trans is
begin
BUF_C: BLOCK(C3 = '1')
begin
Q1_OUT <= guarded A1 when C3 ='1' else "XXXXXXXX";
end BLOCK BUF_C;
end btl;
--------------------------------------------------------------------
library mgc_portable;
use mgc_portable.qsim_logic.all;
-- INIT Entity Description
entity INIT is
port(
A,B: in qsim_state_vector(7 downto 0);
A0,B0: buffer qsim_state_vector(7 downto 0):="00000000";
first_time: buffer qsim_state:='1'
);
end INIT;
-- INIT Architecture Description
architecture rtl of INIT is
begin
INI_process: process
begin
wait for 15ns;
if(first_time = '1') then
A0 <= A;
B0 <= B;
first_time <= '0';
end if;
end process INI_process;
end rtl;