PACKAGES OF MATERIALS FOR THIS CLASS, AVAILABLE IN "SMART COPY"

PACKAGE 1.

 1.
M. Perkowski - How to Do Research.
 2.
Janaka Jayawardena et al - Introduction to EE User Environment.
 3.
Douglas Hall - Mentor Tools tutorial session # 1.
 4.
Douglas Hall - Mentor Tools tutorial session # 2.
 5.
Douglas Hall - Mentor Tools tutorial session # 3.
 6.
How to access Mentor tools.
 7.
David Foote - XACT Development System Tutorial.
 8.
M. Perkowski - EE 572/EE 672 Advanced Logic Synthesis.
Class information.
 9.
Easy intro to VHDL by examples.
 10.
Two level logic, cofactors, Shannon expansion, binary decision diagrams.
 11.
The covering Problem, Petrick Function.
 12.
Satisfiability, Tautology, complementation, using trees in design.
 13.
Approaches to the SOP minimization.
 14.
Design with multiplexers and Ashenhurst Decomposition.
 15.
M.A.  Perkowski J.E. Brown - "A Unified Approach
to Designs Implemented with Multiplexers and to the Decomposition of
Boolean Functions".
 16.
Number of ones circuit.
 17.
Symmetric and Unate Functions. 
 18.
Cube calculus operations.
 19.
VHDL.  Levels of Language constructs: behavioral, data-flow, structural.
 20.
Levels of abstraction.
 21.
Components and instantiations.
 22.
Entity, Architecture, Configuration, Package.
 23.
Library.
 24.
Arrays.

PACKAGE 2.

 1.  Turing Machines
 2.  Parallel State machines,
 3.  Realization of VHDL primitives in hardware.
 4.  Pipelined and parallel processors.
 5.  Satisfiability
 6.  Symmetric Functions.
 7.  Use of invariants in systematic design of a control unit.
 8.  Systematic design of a controller with data path.
 9.  Explanation of homework problems.
 10.  Post logic.
 11.  Take-Home Midterm Examination.
 12.  Student solutions to Homeworks
    - Fibonacci
    - Petrick Machine 

PACKAGE 3.

LECTURE 5.

VHDL continuation.

 1.  Functions
 2.  Wait statement
 3.  Generate Statement
 4.  Synthesis Attributes.
 5.  Finite State Machine.
 6.  Don't care and three state inferencing
 7.  Moore machines
 8.  Mealy Machines.
 9.  Using library units.
 10.  Entity.
 11.  Architecture.

LECTURE 6.

 1. Mini-Project 1.  
 2.  Iterative Logic.
 3.  Logic Design by Inhibition.
 4.  Processes.
 5.  Data-Flow Architectures.
 6.  Structural Architectures.
 7.  Hierarchy of Components.
 8.  Configuration.


LECTURE 7.

 1.  Configuration.
 2.  Primitive elements of VHDL.
 3.  Multi-valued logic, algebras.
 4.  Davio Expansion and introduction to AND/EXOR logic.
 5.  Generalization of Davio Expansion to multiple-valued logic.


LECTURE 8

 1.  Review of Reed-Muller Expansion
 2.  Applications to multi-level logic
 3.  Generalized Orthogonal Expansions.
 4.  VHDL - variables, constants, literals.
 5.  Pipelines.
 6.  Sequential statements.

PACKAGE 4

 1.  Djoikc et al. - "Parallel Algorithms for Generating Subsets and Set Partitions"
 2.  M. Perkowski - Explanation of Mini-Project II.  Fencing State Machines.
 3.  Akl et al - "A simple optimal systolic algorithm for generating permutations."
 4.  Ivan Stojmenovic - "A Simple Systolic algorithm for Generating
     combinations in Lexicographical order".
 5.  Djokic et al.
     - Parallel Algorithms for Generating Subsets and Set Partitions"
 6.  H. Akkary - "A VHDL Simulation Model for a Cube Calculus Machine".
 7.  Coen Engelbarts - The Multiple-valued Cube Calculus Machine Version 2.5.
 8.  Dwaine Franzke, Frank Ma, Jerzy Kolinski - Hough Transform Design.
 9.  Frank Ma - Hough Transform another version.

PACKAGE 5.

VHDL
 
 - processes

 - variables versus signals

 - IF statements

 - CASE statements

 - LOOP statements

 - subprograms

 - conversion functions

 - procedure calls

 - assert statement

 - array types

 - ROM, smart ROM waveform generator

PACKAGE 6

 1.  VHDL
 
 - parametrizable adder/subtracter

 - count zeros circuit

 - drink machine circuit

 - composite types - records

 - aliases
 
 - text and lines

 - signals and signal assignments

 - testbench

 - signal declaration

 - sequential signal assignment hazards

 - simulation cycle

 - concurrent statements

 - concurrent procedure call

 - structural VHDL

   - component instantiation

   - generate statement 

   - configuration

   - generic
 - carry look-ahead example
 
 - serial to parallel converter example

PACKAGE 7

 1.  VHDL
 
 - abstraction
 
 - timing

 - clocking schemes

 - technology independent storage element description

 - partially asynchronous operation

 - asynchronous operation

 - UART example

 - parallel-in, serial-out converter

 - the 2910 architecture

 - roundtrip synthesis

 - VHDL netlist

 - reprocurement

 2.  Class VHDL Project - Jerzy Kolinski - Address Decoder Design.
 3.  Class VHDL Project - Hens Vanderschoot -  Asynchronous State Machines.
 4.  Class VHDL Project - Hens Vanderschoot -  Programmable Deskew Circuit.
 5.  Class VHDL Project - Vance Navarette -  Systolic Sorter.
 6.  Class VHDL Project - Hens Vanderschoot -  Parallel Systolic Sorter.
 7.  Class VHDL Project - Tom Roth -  Systolic Sorter.

PACKAGE 8 

 1.  VHDL:

 - hierarchy

 - configurations

 - generics

 - packages and libraries

 - overloading

 - resolution functions and multiple drivers.

 - symbolic attributes

 2.  Description of the systolic matrix-vector multiplication project.
 3.  Description of the systolic solver of linear equations project.
 4.  Standard Exam questions for Final.

PACKAGE 9.

 1.  Tsutomu Sasao and Marek Perkowski - EXOR logic synthesis.
Chapters 1,2,3,4.

 2.  Drechsler et al,  DAC'95 paper on Ordered Kronecker Functional Decision Diagrams.

 3.  Perkowski et al, Journal of VLSI paper on
" Multi-level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean
Ternary Decision Diagrams for Incompletely Specified Functions."

 4.  A. Sarabi, M. Perkowski, " Design for
     Testability Properties of AND/EXOR Networks".
 5.  Ning Song, M. Perkowski, "A New Design Methodology for
     Two-Dimensional Logic Arrays".
 6.  Wei Wan, M. Perkowski , EURO-DAC '92 paper on TRADE decomposition.
 7.  A.  Sarabi et al, DAC'94 paper on two-dimensional logic arrays.
 8.  Perkowski et al, "Application of Orthogonal Transforms in Image Processing".
 9.  Pierzchala, Perkowski, Grygiel,  ISMVL'94 paper on Field Programmable Analog Array.
 10.  Pierzchala, Perkowski,  Transparencies on Field Programmable Analog Arrays.
 11.  Song et al, "A New Design Methodology for Two-Dimensional Logic Arrays".
 12.  Haomin Wu et al "Generalized Partially-Mixed-Polarity Reed-Muller
     Expansion and its Fast Computation."

PACKAGE 10.

 1.  Wei Wan - Transparencies on TRADE decomposition.
 2.  Bernd Steinbach - Data Structures and Algorithms for Solving
Very Large Boolean Problems,
and Design of Circuits Using Decomposition Methods.

Steinbach's (XBOOLE) AND/OR/EXOR decomposition.

 3.  Marek Perkowski - Transparencies on Binary Orthogonal Logic.
     Universal cells. Generalized PLAs.
 4.  Robert C. Minnick - A Survey of Microcellular Research.
 5.  Marek Perkowski - Transparencies on Multiple-Valued Orthogonal Logic.
 6.  Haomin Wu, Marek Perkowski, Nan Zhuang - Synthesis of MUX DAG Network
     with Application to FPGAs and BDDs.
 7.  Marek Perkowski - Transparencies on Families of Canonical AND/EXOR forms.
 8.  Marek Perkowski - Self-Evaluation Questionaire.
 9.  Tsutomu Sasao/Marek Perkowski - Transparencies from Chapter 2 of EXOR logic book.

PACKAGE 11.

 1.  M. Perkowski - SREP Proposal to Air Force Office of Scientific Research.
Functional Decomposition of Binary, Multiple-valued and Fuzzy logic
for Applications in Pattern Theory.

This is a guidelines for us what we are supposed to do.
Also, list of decomposition literature with 443 positions.

 2.  Transparencies for "Decomposition of Information Systems Using Decision Tables."
This paper is easier to understand that other Luba's papers and has also no errors.
It has good link to automatic knowledge acquisition in expert systems.

 3.  Perkowski - presentation about decomposition from the point of
view of future research at Wright Labs.

 4.  Selvaraj, Luba et al, - "A Generalized Decomposition of Boolean
Functions and its Application in FPGA-based Synthesis."

 5.  Luba and Lasocki - "Decomposition of Multiple-valued Boolean Functions".
Take care - many errors.

 6.  Transparencies according to Kandel and Francioni.
This paper is good starting point to fuzzy
logic, but decomposition is now obsolete.

 7.  Wei Wan - Master thesis about TRADE and decomposition.
Read this first.  Try to change from maps and/or cubes to BDDs.
Many good ideas.

 8.  Selvaraj - Ph.D thesis on serial/parallel  decomposition.
The most recent explanation of Luba's approach, but not very well written.
Many good examples. 

 9.  Pedram et al. - DAC '93 paper on Curtis decomposition for
multiple-output, incomplete functions based on standard BDDs and
ternary BDDs (with dont;t cares).  Many errors.  Idea of cut
in BDD being the same as multiplicity index.

 10.  Luba et al - Decomposition of Information Systems
Using Decision Tables. Good paper.
Reed it as first Luba paper.

 11.  Pedram et al. - Logic Synthesis using Multiple-Output Function Decomposition.
Better explanation than DAC'93. Beware of errors.

 12.  Craig Files, - Using a search heuristics in an NP-complete problem in
Ashenhurst-Curtis Decomposition.
Idea of step-by-step selection of variables for bound set.
Very good, can be further improved with better function representation.
Can be also extended to multiple-valued functions.
 13.  Francioni and Kandel - the first paper in fuzzy decomposition.  Good literature and intro.

 14.  Tsutomu Sasao - "FPGA design by Generalized Functional Decomposition"
Historically valid. good examples, easy to read.

PACKAGE 12.

 1.  Designer's views mixed on analog HDLs.

 2.  EE 573 FPAA Project Topics.

 3.  E. Pierzchala, M. Perkowski, Field Programmable Analog Arrays (FPAAs). Transparencies.

 4.  IMP's EPAC IMP50E10. Data sheet of the first commercial FPAA.

 5.  E. Pierzchala, M. Perkowski, High Speed
Field Programmable Analog Arrays (FPAAs) Architecture Design. Transparencies.

 6.  E. Pierzchala et al., "Current-Mode Amplifier/Integrator for a 
Field-Programmable Analog Array".

 7.  Salter et al.
Analogix Corporation's Analog Cell.

 8.  Lee and Gulak, - "MOS Transconductor Based Field-Programmable Analog Array".

 9.  Frank Goodenough - "Analog Counterparts of FPGAs Ease System Design".

PACKAGE 13.

 1.  Perkowski - A Survey of Literature on Function Decomposition, report to WL. Sept. 1994.

 2.  Perkowski - EE 573. Class Projects and Topics for presentation.
     Explanation of decomposition projects.

 3.  Bryant and Chen - "Verification of arithmetic functions with Binary Moment Diagrams.

 4.  Perkowski -  Class Transparencies on Tree and Heuristic Search.
     This  should help you in programming tree search algorithms
     for graph coloring, set covering, assignment/encoding, variable partitioning and so on.

 5.  Perkowski et al - Book chapter - Rapid Software Prototyping for CAD.  The same in full form.

 6.  Information on software packages POLO and Espresso in 
     directory /stash/polo.

 7.  Jeff Goldman - Pattern Theoretic Knowledge Discovery.
     Explains functional decomposition from the machine learning point of view.

PACKAGE 14.

 1.  Transparencies about ESOP minimizers, especially EXORCISM-MV-2 by Ning Song.

 2.  Helliwell and Perkowski - DAC'88 paper about first efficient ESOP minimizer.
     Now only of historic value, but easy to understand and many examples
     to practice.
 3.  Perkowski and Chrzanowska - "An Exact Algorithm
     to Minimize Mixed-Radix..... - the first exact ESOP minimizer
     from 1990. Since then superseded by Sasao and Koda.

 4.  Lecture notes on possible improvements to our ESOP exact minimizer program. 

 5.  The contents of directory /stash/polo
 
      - cgrmin man pages
      - TRADE man pages
      - act map man pages
      - MIS II programs man pages

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