DIGITAL DESIGN WITH VHDL AND VERILOG

Marek A. Perkowski, Professor EE

School of Enginering and Applied Science

Department of Electrical Enginering

• This class started in 1990. It was deeply modified VHDL in 1994. The class has been modified according to opinions of industrial students. More practical examples were added, less about language syntax. More various types of student homeworks and mini-projects. One large project is no longer mandatory, but still possible for volunteers.
• Grading is based on two homeworks and final project. Volunteers can have one larger project. No exams.
• Much time is now given to fundamental aspects of logic synthesis and VHDL-related design automation that are already commonly used in industry. Tools from industry, Mentor, Cypress, Summit, and Orcad, are presented and used in the projects. System-related subjects are discussed that are of personal interest to students. Verilog project can be selected by a student, but only small time is allocated in class for Verilog syntax.
• Students can propose their own group or individual projects. There will be at least three different projects related to VHDL logic synthesis to choose from.
• This course can be taken as a part of Design Automation sequence.
• Most time will be spend to teach VHDL language on a sequence of carefully selected progressively more difficult examples, for both specification, simulation and synthesis. System-related subjects will be discussed that are of interest to students. A new book written by Cypress engineer will be used in addition to previous books and instructor's lecture notes and journal/conference papers. Lecture notes will be also available.
  The class has been now made independent and it does not require other classes as prerequisities.

  TEXTBOOKS: this quarter the standard textbooks are:

• 1. Stanley Mazor, Patricia Langstraat - A Guide to VHDL. Kluwer Academic Publishers. (This is an easy to use textbook on VHLDL from Synopsys company, with many ready to run good examples. Students will also use Mentor manuals in their projects. Several other VHDL textbooks are also available from the professor).
• 2. Kevin Skahill, VHDL for Programmable Logic, Cypress Semiconductor, Addison-Wesley, 1996.
• 3. Zvi Kohavi - Switching and Finite Automata Theory. (This is a classical graduate textbook on switching circuits and state machines. Although material is somewhat outdated, it provides an excellent introduction to the subject and theory. Modern information will be upgraded from catalogs, newer textbooks and journal/conference publications that will be available from SmartCopy).
• We will also use lecture notes by Marek Perkowski. They will be available from Reserve Library at PSU and from SmartCopy. (SmartCopy is located two block up from PCAT, on right, opposite to the ONDINE dormitory).
  The address is:
  1915 S.W. 6th Avenue, Portland, OR 97201.
  tel. (503) 227-6137.
• Please send me email if you have any questions.
• In the past, students successfully designed a microprocessor, DSP processor and several controllers. However, the difficulty of the project this year will depend on student preferences and level of skills that they will represent. Both simple and more advanced projects will be available.
• This class is not as difficult as was the class before, it is really recommended to less advanced students, and I will make an effort to explain all fundamental things, if necessary.