//
//  FlexTest  v8.4_1.17    Fri Sep 30 22:56:14 PDT 1994
//  Design Name = /usr3/local_user/lixin/ccm/state
//  Total Test Cycles = 30
//  Time = Tue May  2 11:49:58 1995
//   
//  *****Circuit Statistics*****
//  # of primary inputs = 7
//  # of primary outputs = 4
//  # of library model instances = 2
//  # of netlist primitive instances = 22
//  # of combinational gates = 26
//  # of sequential elements = 2
//  # of simulation primitives = 75
//   
//  *****Fault List Statistics*****
//  Fault Class              Uncollapsed   Collapsed
//  Full (FU)                        180          90
//  Det_simulation (DS)              167          79
//  Hyp_testable (HT)                  7           5
//  Tied (TI)                          2           2
//  Atpg_untestable (AU)               1           1
//  Unobserved (UO)                    3           3
//  Fault coverage                94.72%      90.56%
//  Test coverage                 95.79%      92.61%
//  ATPG effectiveness            96.39%      93.89%
//   
//  *****Test Patterns Statistics*****
//  Total Test Cycles Generated = 30
//  Total Test Cycles Simulated = 30
//  
//  ***** Runtime Statistics *****
//  Machine Name    : sunburn
//  User Name       : lixin
//  User CPU Time   : 2.1 seconds
//  System CPU Time : 1.0 seconds
//  Memory Used     : 5.598M
//  
//
//  Settings:
//  Abort Limit = (backtrack=30, cycle=300, time=300 seconds)
//  Checkpoint = off
//  Clock Restriction = on
//  Contention Check = (bus=(0,noatpg,warning), port=off)
//  Fault Sampling = 100%
//  Fault Type = stuck_at
//  Gate Level = design
//  Gate Report = normal
//  Hypertrophic Limit = 30%
//  Iddq Checks = none, noatpg, warning
//  Iddq Strobe = label
//  Identification Model = (clock=original, disturb=on)
//  Internal Faults = on
//  Loop Handling = hold
//  Net Dominance = wire
//  Net Resolution = wire
//  Pin Constraints (default) = type NR, period 1, offset 0
//  Pin Strobes (default) = 1
//  Possible Credit = 50%
//  Pulse Generators = on
//  Random ATPG = on
//  Scan Identification = automatic  Internal  Full
//  State Learning = on
//  Test Cycle Width = 1
//  Tied Signal = x
//  Trace Report = off
//  Z Handling = (external=x, internal=x)

SETUP =

    TEST_CYCLE_WIDTH = 1;

    DECLARE INPUT BUS "ibus" = "/PRIME", "/RIGHT_EDGEI", "/NEXTI", "/W",
                      "/CLEAR", "/VARIABLE", "/REQUEST";
    DECLARE OUTPUT BUS "obus_1" = "/SLCT0", "/SLCT1", "/READY", "/NEXTI+1";

END;

CYCLE_TEST =

    CYCLE = 0;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 1;

    FORCE "ibus" "0111010" 0;
    MEASURE "obus_1" "0011" 1;

    CYCLE = 2;

    FORCE "ibus" "0011001" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 3;

    FORCE "ibus" "0001100" 0;
    MEASURE "obus_1" "0000" 1;

    CYCLE = 4;

    FORCE "ibus" "0110000" 0;
    MEASURE "obus_1" "0001" 1;

    CYCLE = 5;

    FORCE "ibus" "0001011" 0;
    MEASURE "obus_1" "0100" 1;

    CYCLE = 6;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 7;

    FORCE "ibus" "0111010" 0;
    MEASURE "obus_1" "0011" 1;

    CYCLE = 8;

    FORCE "ibus" "0011001" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 9;

    FORCE "ibus" "1010010" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 10;

    FORCE "ibus" "0110001" 0;
    MEASURE "obus_1" "0101" 1;

    CYCLE = 11;

    FORCE "ibus" "1111000" 0;
    MEASURE "obus_1" "0001" 1;

    CYCLE = 12;

    FORCE "ibus" "1101011" 0;
    MEASURE "obus_1" "1000" 1;

    CYCLE = 13;

    FORCE "ibus" "1010010" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 14;

    FORCE "ibus" "0110011" 0;
    MEASURE "obus_1" "0110" 1;

    CYCLE = 15;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 16;

    FORCE "ibus" "1000010" 0;
    MEASURE "obus_1" "1000" 1;

    CYCLE = 17;

    FORCE "ibus" "0110011" 0;
    MEASURE "obus_1" "0010" 1;

    CYCLE = 18;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 19;

    FORCE "ibus" "0111010" 0;
    MEASURE "obus_1" "0011" 1;

    CYCLE = 20;

    FORCE "ibus" "0011001" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 21;

    FORCE "ibus" "1100010" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 22;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 23;

    FORCE "ibus" "0111010" 0;
    MEASURE "obus_1" "0011" 1;

    CYCLE = 24;

    FORCE "ibus" "1000001" 0;
    MEASURE "obus_1" "0001" 1;

    CYCLE = 25;

    FORCE "ibus" "1111010" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 26;

    FORCE "ibus" "0101000" 0;
    MEASURE "obus_1" "1000" 1;

    CYCLE = 27;

    FORCE "ibus" "1011111" 0;
    MEASURE "obus_1" "1001" 1;

    CYCLE = 28;

    FORCE "ibus" "0100000" 0;
    MEASURE "obus_1" "0000" 1;

    CYCLE = 29;

    FORCE "ibus" "0011011" 0;
    MEASURE "obus_1" "0001" 1;

END;