VHDL CLASS



This is Official Web Page of Digital Design using Hardware Decription Languages Class, taught by Marek Perkowski.

The class teaches digital design, VHDL and Verilog. New design systems and tools are also discussed. There are many resources on this webpage, but you do not need to look into all directories. At the beginning, look only to the directories from the section "Information for Spring 2017 Class" below.




INFORMATION FOR SPRING 2017 CLASS

  1. Slides from lectures and additional reading assigned for each meeting of a class. For year 2017. Class schedule. This page is regularly updated, check it.

  2. How to use Modelsim tools.

  3. Grading.

  4. Books.




GENERAL INFORMATION FROM PREVIOUS CLASSES.

  1. Slides from lectures 2006. Class schedule.

  2. General Description of the class.

  3. Standard past questions asked by students and answers.

  4. Questions and answers Answers to questions about this class.


  5. Official Class Description from the old catalog. Since then, Verilog and more design and computer architecture material has been added.

  6. A general introduction and a contents of Smart Copy box with our class material. This is auxiliary information, since now much of this material is on the Web for either this or other classes that I teach.

  7. Past project information.




VHDL AND TOOLS' PRIMERS

  1. VHDL Primers and all introductory information. This is for people who have not taken ECE 271 class and labs at PSU.

  2. VHDL and Fast Protyping Courses from Pennsylvania State University. Set of Slides in PowerPoint, student projects and other interesting materials

  3. VHDL slides from Penn State for Lecture 1 (module 10).

  4. All VHDL modules (11,12,13,60)

BOARDS AND RECONFIGURABLE COMPUTING

  1. Information about DEC-PERLE-1 board and projects using it.

ADDITIONAL INFORMATION ABOUT MENTOR TOOLS.

  1. VHDL resources of ECE 271.

  2. Mentor Graphics WWW Page

BOOKS, WEB PAGES AND OTHER RESOURCES:

  1. Books about VHDL available on Internet.
  2. VHDL Resources: Textbooks, pages, projects, programs.

EXAMPLES OF PAST VHDL HOMEWORKS AND MINI-PROJECTS:



The goal of this homeworks two is to learn how to design a standard controller (Glushkov Machine) composed of a Finite State Machine controlling the Data Path (this can be a Mealy Machine, a Moore Machine, a Petri Net or a combination of machines) and the Data Path. The Data Path includes Input/Output and Memories.

  1. Final Class Homeworks and Projects Done in 2002.

  2. Projects Proposed by Marek Perkowski for year 2002.
  3. Sorter.

  4. Various sorters for homeworks 1 and 2.

  5. The LCM machine.

  6. Minimum Selector. Simulation only.

  7. Another variant of Minimum Selector. Design for synthesis and discussion of synthesis results. Xilinx tools.

  8. Running Sum from Mentor's demo. Simulation.

  9. Running Sum from Mentor's demo. Synthesis.

  10. Fibonacci Sequence Generator Machine.

  11. Greatest Common Divisor machine.

  12. GCD Machine Report

    1. Synopsys VSS simulator setup file: synopsys_vss.setup.
      remember that this file is .synopsys_vss.setup with dot at the beginning.

      If synopsys tools are installed, this script can be used to automatically compile and simulate the testbench:
    2. gcd.csh

    3. Sub circuits used by the GCD circuit: gcdcomp.vhd
    4. Top level gcd circuit: gcd.vhd
    5. Test Benches for test GCD components and the GCD circuit: comptest.vhd
    6. Simulation Command File: comptest1.scr


  13. Another GCD Machine

  14. Waveform generator.

  15. Unate function checker controller.

  16. Petrick Function Machine.

EXAMPLES OF PAST VHDL FINAL PROJECTS:

  1. Floating Point Processor.

  2. General Purpose Processor Realized Using Reversible Logic. Processor for extremely low power.

  3. Cube Calculus Machine. This is a special purpose computer for solving combinatorial decision and optimization problems. Several versions exist.
  4. Text of Qihong Chen and Figures. Latex and eps formats.

  5. Decomposition Machine project. This is a computer to learn in hardware using the Ashenhurst/Curtis Decomposition.

  6. Satisfiability Machine. This machine solves the satisfiability formula in hardware. Various variants of this machine has been designed in previous classes. CODE NOT HERE.

  7. Rough Set Theory Machine This machine is a cellular processor to process rough sets from the Pawlak's Theory used in Data Mining.

  8. Image Processing and Pattern Recognition computer. Processors for various image processing and pattern recognition tasks. They have been never put together to one complete system.

  9. Automatic BIST insertion to VHDL code project. This project is about using testability tools. You take any controller and insert BIST. Then you analyze testability and generate tests.

  10. Controlled Delay circuit. This is a practical circuit which is perhaps the simplest of all final VHDL projects in this class.

  11. Square Root Processor. This is another example of a simple final project.

  12. Complete RISC CPU. One of the most complex projects ever done in this class. Complete chip was simulated and designed.

  13. Robot. Very simple robot controller. Many useful remarks about using VHDL tools from Mentor.

  14. Double Processor. Cube Calculus Machine and Motorola Microcontroller combined. CODE NOT HERE.

  15. TIC-TAC-TOE machine.
    1. Phil Beutz , and Hua Yong Zhong CODE NOT HERE.

  16. MACHINE FOR THE COVERING PROBLEM.
    This is a more advanced variant of the machine from the class. Similar to project above, Petrick machine and Satisfiability Machine.
    AUTHORS: Vurkac Mehmet (Group Leader), Lecca Leonardo Jose, CODE NOT HERE.

  17. Unit 3, part 5




PAST PROJECT ASSIGNMENTS:

  1. 2001. Short description of projects.

  2. 2001. Long description of projects: ideas, people, deadlines, deliverables.

  3. Year 2000.




MORE INFORMATION ON VERILOG:

  1. Look here for more information.



EXAMPLES OF PAST VERILOG FINAL PROJECTS:

  1. Spread Spectrum Communication System.



EXAMPLES OF PAST LOGIC SYNTHESIS USING VHDL TOOLS:

  1. Sorter Circuit synthesized using Leonardo tool.