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PUBLICATIONS

A
  1. actel
    ``ACT Family Field Programmable Gate Array Data Book,'' March 1991. ACTEL
    .

    AKERS
  2. akers59
    S. B. Akers, ``On a Theory of Boolean Functions'', Journal of SIAM
    , vol. 7, pp. 487-498, Dec. 1959.

  3. akers78
    S.B. Akers, ``Binary Decision Diagrams,'' IEEE Trans. on Computers,
    Vol. C-27, No. 6, pp. 509-516, June 1978.

  4. algotronix
    Algotronix, ``The CHS 2*4, The world's first custom computer'',
    Algotronix Ltd,
    Kings Buildings - TTC, Mayfield Road, Edinburgh EH9 3JL, Scotland, 1992.

    ALMAINI

  5. almaini77
    A. E. A. Almaini, and M. E. Woodward, ``An Approach to the Control Variable Selection Problem for Universal Logic Modules,''
    Digital Processes,
    Vol. 3, pp. 189-206, 1977.

  6. almaini91
    A.E.A. Almaini, P. Thomson, D. Hanson, ``Tabular techniques for Reed-Muller logic,''
    Int. J. Electron.
    (UK), vol.70, no.1, 23-34, Jan. 1991.

    AOKI

  7. aoki84
    K. Aoki, S. Watanabe, ``Efficient digital calculation circuit,''
    IBM Tech. Disclosure Bull.
    (USA), vol.27, no.7A, 4019-20, Dec. 1984.

    AREITIO-BERTOLIN

  8. areitio88
    J. Areitio-Bertolin, M.G. Areitio-Bertolin, ``Formulation of digital structures through formats based on the EXOR operator,''
    Rev. Esp. Electron.
    (Spain), no.400, 104-6, March 1988.

    ARTIN

  9. artin57
    E. Artin, Geometric Algebra

    Interscience Publishers, Inc., 1957.
    B


    BANDYOPADHYAY

  10. bandyopadhyay
    S. Bandyopadhyay, A. Pal, A. K. Choudhury,
    ``Characterization of Unate Cascade Realizability Using Parameters,''
    IEEE Trans. on Comput.,
    Vol. 24, No. 2, pp. 218-219, February 1975.

    BEAUCHAMP

  11. beauchamp84
    K. G. Beauchamp,
    ``Applications of Walsh and Related Functions,''
    Academic Press,
    New York, 1984.

  12. beauchamp87
    K. G. Beauchamp, ``Transforms for Engineers, A Guide to Signal Processing,
    Clarendon Press, Oxford, 1987.

    BECKER

  13. becker95
    Bernd Becker and Rolf Drechsler How many Decomposition Types do we need?
    IEEE European Design & Test Conference, pp. 438-443, Paris, 1995


  14. becker96ac
    Bernd Becker, Rolf Drechsler, Rolf Krieger and Sudhakar M. Reddy, A Fast Optimal Robust Path Delay Fault Testable Adder
    IEEE European Design & Test Conference, pp. 491-498, Paris, 1996


  15. becker95
    Bernd Becker, Rolf Drechsler and Ralph Werchner
    On the Relation between BDDs and FDDs
    Information and Computation, Volume 123, pp. 185-197, December 1995


  16. drechsler97a
    B. Becker, R. Drechsler and M. Theobald
    On the Expressive Power of OKFDDs
    Formal Methods in System Design: An International Journal, 1997


  17. becker-report-93
    B. Becker, R. Drechsler, and R. Wechner, ``On the Relation Between BDDs and FDDs,'' Technical Report
    , University of Frankfurt, 12/93, 1993.

  18. becker-reed93
    B. Becker, R. Drechsler, M. Theobald, ``On the Implementation of a Package for Efficient Representation and Manipulation of Functional Decision Diagrams,'' Reed-Muller Proceedings,
    1993.

    BEDARIDA

  19. bedarida92
    A. Bedarida, S. Ercolani, and G. DeMicheli,
    ``A New Technology Mapping Algorithm for the Design and Evaluation of Fuse/Antifuse-based Field-Programmable Gate Arrays,'' Proc. 1st ACM Workshop on FPGAs,
    pp. 103-108, February 1992, Berkeley, CA.

    BENJAUTHRIT

  20. benjauthrit-Reed76
    B. Benjauthrit, I.S. Reed,
    ``Galois switching functions and their applications,'' IEEE Trans. Comput.
    (USA), vol.C-25, no.1, 78-86, Jan. 1976.

  21. benjauthrit??
    B. Benjauthrit,
    ``Design and diagnosis of Galois logic networks,'' ******

    BENNETTS

  22. bennett71
    R. G. Bennetts, and D. Lewin,
    ``Fault diagnosis of digital systems - a review,'' Comput. J.,
    vol. 14., pp. 199-206, 1971.

    BENNETT

  23. bennett78
    L. A. M. Bennett,
    ``The Application of Map-Entered Variables to the Use of Multiplexers in the Synthesis of Logic Functions,''
    Int. J. Electronics,
    Vol. 45, No. 4, 1978, pp. 373-379.

    BESSLICH

  24. besslich83
    Besslich, P.W., ``Efficient computer method for ExOR logic design,'' IEE Proc. E
    (GB), vol.130, no.6, 203-6, Nov. 1983.

  25. besslich91
    Besslich, P.W., Riege, M.W.,
    ``An efficient program for logic synthesis of mod-2 sum expressions,'' Euro ASIC '91,
    (Cat. No.91TH0367-3), 136-41, xii+396, 1991, IEEE Comput. Soc. Press, Los Alamitos, CA, USA.

  26. besslich-euroasic91
    Ph.W. Besslich, M.W. Riege
    "An Efficient Program for Logic Synthesis of Mod-2 Sum Expressions,"
    Proc. Euro ASIC'91, pp. 136-141, Paris, France, 1991.

  27. besslich-riege92
    P. W. Besslich, M.W. Riege, ``Low-complexity synthesis of incompletely specified multiple-output mod-2 sums,'' IEE Proc. E, Comput. Digit. Tech.
    (UK), vol.139, no.4, 355-62, July 1992.

    BESSON

  28. BESS92
    T. Besson, H. Bousouzou, M. Crates, G. Saucier,
    ``Synthesis on Multiplexer-based Programmable Devices Using (Ordered) Binary Decision Diagrams,'' Proc. EURO-ASIC,
    pp. 8-13, June 1992, Paris, France.

  29. Besson-92-icccd
    T. Besson, H. Bousouzou, M. Crastes, G. Saucier,
    ``Synthesis on Multiplexer-based F.P.G.A. Using Binary Decision Diagrams,'' Proc. of IEEE ICCD
    , pp. 163-167, 1992.

    BHATTACHARYA

  30. bhattacharya84
    B. B. Bhattacharya, B. Gupta, S. Sarkar, A. K. Choudhury,
    ``Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults,''
    Comput. & Electr. Eng.
    (USA), vol.11, no.1, 67-78, 1984.

  31. bhattacharya85
    B. B. Bhattacharya, B. Gupta, S. Sarkar, A. K. Choudhury,
    ``Testable design of RMC networks with universal tests for detecting stuck-at and bridging faults,''
    IEE Proc. E
    (GB), vol.132, no.3, 155-62, May 1985.

    BRAND

  32. BRAND93
    D. Brand and T. Sasao, "Minimization of AND-EXOR expressions using rewriting rules," IEEE Transactions on Computers, Vol. 42, No. 5 May 1993, pp. 568-576.

    BRAYTON

  33. BRAY89
    R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, A. R. Wang, ``MIS : Multi-Level Interactive Logic Optimization System,''
    IEEE Trans. on CAD,
    Vol. 6, No. 6, 1989, pp. 1062-1082.

  34. BRAY90
    R. K. Brayton, G. D. Hachtel, A. L. Sangiovanni-Vincentelli,
    ``Multilevel Logic Synthesis,'' Proc of the IEEE
    , Vol. 78, No.2, pp. 264-300, February 1990.

  35. brigham74
    E. O. Brigham, ``The Fast Fourier Transform,''
    Prentice Hall,
    1974.

    BRYANT

  36. Bryant86
    R. E. Bryant, ``Graph-Based Algorithms for Boolean Function Manipulation,''
    IEEE Trans. on Comput.
    , Vol. 35, No. 8, pp. 667-691, August 1986.
    BUTLER

  37. butler
    K. M. Butler, D. E. Ross, R. Kapur, M. R. Mercer,
    ``Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams,''
    Proc. 28th ACM/IEEE DAC,
    pp. 417-420, 1991.
    C


    CHEN

  38. chen92
    K.~C. Chen, ``Logic Minimization of Lookup-Table Based FPGAs,''
    Proc. 1st ACM Workshop on FPGAs,
    pp. 71-76, February 1992, Berkeley, CA.
    PAIK

  39. chul-chong81
    Ch. H. Paik, Ch. S. Kim,
    ``RMC forms determination with minimal literals and test sets,''
    J. Korea Inst. Electron. Eng.,
    vol.18, no.3, 9-14, June 1981.

    CLARKE

  40. clarke93
    E. M. Clarke, X. Zhao, M. Fujita, Y. Matsunaga,
    ``Fast Walsh Transform Computation with Binary Decision Diagrams,''
    Reed-Muller Proceedings
    , 1993.

  41. clarke93a
    E. M. Clarke, K.L. McMillan, X. Zhao, M. Fujita,
    `` Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping,''
    Reed-Muller Proceedings
    , 1993.

  42. CONC91
    Concurrent Logic Inc,
    "CLi6000 Series Field Programmable Gate Array,"
    Preliminary Information,
    December 1991.


    COY

  43. coy79
    W. Coy, ``On the design of easily testable iterative systems of combinational cells,'' IEEE Trans. Comput.
    (USA), vol.C-28, no.5, 367-71, May 1979.

    CSANKY

  44. csanky-perkowski-schaefer92
    L.~Csanky, M.~A.~Perkowski, and I.~Schaefer,
    ``Canonical restricted mixed-polarity exclusive sums of products,''
    1992 IEEE International Symposium on Circuits and Systems,
    (Cat. No.92CH3139-3), 17-20, vol.1, 6 vol. 3028, 1992, IEEE, New York, NY, USA.

  45. csanky93


  46. CSA93
    L.~Csanky, M.~A.~Perkowski, and I.~Schaefer,
    ``Canonical restricted mixed-polarity exclusive-OR sums of products and the efficient algorithm for their minimisation,''
    IEE Proc. E, Comput. Digit. Tech.
    (UK), vol.~140, no.1, pp.~ 69-77, Jan. 1993.
    D


    DAMARLA

  47. damarla89
    T. R. Damarla,
    ``Fault detection in Reed-Muller canonical (RMC) networks,''
    SOUTHEASTCON '89 Proceedings. Energy and Information Technologies in the Southeast,
    (Cat. No.89CH2672-4), 192-6 vol.1, 3 vol. xxvi+1448, 1989, IEEE, New York, NY, USA.

  48. damarla-karpovsky89
    T. R. Damarla, M. Karpovsky,
    ``Fault detection in combinational networks by Reed-Muller transforms,''
    IEEE Trans. Comput.
    (USA), vol.38, no.6, 788-97, June 1989.

  49. damaria-karpovsky
    T. Damaria, M. Karpovsky,
    ``Detection of stuck-at and bridging faults in Reed-Muller canonical (RMC) networks,''
    IEE Proc. E, Comput. Digit. Tech.
    (UK), vol.136, no.5, 430-3, Sept. 1989.

    DAMM

  50. damm93
    C. Damm,
    `` ExOR vs. OR: Feasability for Symmetric Functions,''
    Reed-Muller Proceedings
    , 1993.

  51. damm93a
    C. Damm,
    ``How much ExOR Improves on OR?,''
    Reed-Muller Proceedings
    , 1993.

    DAVIO

  52. DAV78
    M.~Davio, J-P.~Deschamps, and A.~Thayse,
    Discrete and Switching Functions
    , McGraw-Hill International, 1978.

    DAVIDHEISER

  53. davidheiser92
    R.~ Davidheiser,
    ``High $T sub c$ superconducting digital gates,''
    Proc. SPIE - Int. Soc. Opt. Eng. (USA),
    vol.1597, 87-9, 1992.

    DEBNATH

  54. debn96
    D. Debnath and T. Sasao, "Minimization of AND-OR-EXOR three-level networks with AND gate sharing," the Sixth Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'96), Fukuoka, Japan, Nov. 25-26, 1996, pp. 67-73.

  55. debn96a
    D. Debnath and T. Sasao, "GRMIN2: A heuristic simplification algorithm for generalized Reed-Muller expressions," IEE Proceedings, Computers and Digital Techniques, Vol. 143. No.6, Nov. 1996, pp.376-384.

  56. debn97b
    D. Debnath and T. Sasao,"An Optimization of AND-OR-EXOR three level networks," Asia and South Pacific Design Automation Conference (ASPDAC'97), Makuhari, Japan, pp. Jan. 1997, pp.545-550.

  57. debn95b
    D. Debnath and T. Sasao, "GRMIN: A heuristic minimization algorithm for generalized Reed-Muller expression," IFIP WG 10.5 Workshop on Applications of the Reed-Muller Expansions in Circuit Design (Reed-Muller '95), Makuhari, Japan. Aug. 27-29, 1995.

  58. debn95
    D. Debnath and T. Sasao, "GRMIN: A heuristic minimization algorithm for generalized Reed-Muller expression," Asia and South Pacific Design Automation Conference (ASPDAC'95), Aug. 29-Sept. 1, Makuhari, Japan, pp. 341-347.

  59. debn95a
    D. Debnath and T. Sasao, "An optimization of AND-OR-EXOR three-level expressions by table look-up," Technical Report. IEICE Japan, VLD95-91, pp. 9-16, Oct. 1995.

  60. debn97a
    D. Debnath and T. Sasao, "Minimization of AND-OR-EXOR three-level networks with AND gate sharing," IEICE Trans. 1997 (accepted).

  61. debn97
    D. Debnath and T. Sasao, "Exclusive-OR of two sum-of-products expressions: simplification and an upper bound on the number of products," Proc. 3rd International Workshop on Applications of the Reed-Muller Expansion in Circuit Design (Reed-Muller'97), Oxford, U.K., pp. 45-60, Sept. 19-20, 1997.

    DRECHSLER

  62. drechsler94
    R. Drechsler, and B. Becker,
    `` Rapid Prototyping of Fully Testable Multi-Level AND/ExOR Networks,''
    Reed-Muller Proceedings
    , 1993.

  63. drechsler94-dac
    R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M.A. Perkowski,
    ``Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams,''
    Proceedings of DAC '94
    , San Diego, CA, June 1994.

  64. drechsler97
    R. Drechsler, B. Becker and S. Ruppertz
    K*BMDs: A New Data Structure for Verification
    IEEE Design & Test, Summer 1997


  65. drechsler97b
    R. Drechsler and B. Becker
    An Overview on Decision Diagrams
    IEE Proceedings Computers and Digital Techniques, 1997


  66. drechsler97c
    R. Drechsler and B. Becker
    Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 16, Number 1, pp. 1-5, January 1997


  67. drechsler96
    R. Drechsler, B. Becker and N. G"ockel
    A Genetic Algorithms for Variable Ordering of OBDDs
    IEE Proceedings Computers and Digital Techniques
    Volume 143, Number 6, pp. 364-368, November 1996


  68. drechsler96a
    Rolf Drechsler, Michael Theobald and Bernd Becker
    Fast OFDD based Minimization of Fixed Polarity Reed-Muller Expresssions
    IEEE Transactions on Computers, Volume 45, Number 11, pp. 1294-1299, November 1996


  69. drechsler95
    Rolf Drechsler, Bernd Becker, Nicole G"ockel and Andrea Jahnke
    A Genetic Algorithm for Decomposition Type Choice in OKFDDs
    International Journal on Artificial Intelligence Tools, Volume 4, Number 4, pp. 525-536, December 1995


  70. drechsler95c
    Bernd Becker, Rolf Drechsler and Paul Molitor
    On the Generation of Area-Time Optimal Testable Adders
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 14, Number 9, pp. 1049-1066, September 1995


  71. drechsler96b
    Rolf Drechsler and Bernd Becker
    OKFDDs - Algorithms, Applications and Extensions
    In: Representation of Discrete Functions, edited by T. Sasao and M. Fujita,
    Kluwer Academic Publisher, pp. 163-190, 1996.


  72. drechsler96d
    Rolf Drechsler, Bernd Becker and Stefan Ruppertz
    Manipulation Algorithms for K*BMDs
    Tools and Algorithms for the Constuction and Analysis of Systems, LNCS 1217, pp. 4-88, Enschede, 1997


  73. drechsler97d
    Rolf Drechsler, Harry Hengster, Horst Sch"afer, Joachim Hartmann and Bernd Becker Testability of 2-Level AND/EXOR Circuits
    IEEE European Design & Test Conference, pp. 548-553, Paris, 1997.

  74. drechsler97aa
    Rolf Drechsler, Bernd Becker and Nicole G"ockel A Genetic Algorithm for the Construction of Small and Highly Testable OKFDD Circuits
    Genetic Programming, Stanford, 1996


  75. drechsler96aa
    Rolf Drechsler, Nicole G"ockel and Bernd Becker Learning Heuristics for OBDD Minimization by Evolutionary Algorithms
    Parallel Problem Solving from Nature, Berlin, 1996


  76. drechsler96ab
    Rolf Drechsler, Bernd Becker and Nicole G"ockel Minimization of OKFDDs by Genetic Algorithms
    International Symposium on Soft Computing, Reading, 1996


  77. drechsler96ac
    Rolf Drechsler, Bernd Becker and Stefan Ruppertz
    K*BMDs: A New Data Structure for Verification
    IEEE European Design & Test Conference, pp. 2-8, Paris, 1996


  78. drechsler96ad
    Rolf Drechsler and Bernd Becker Dynamic Minimization of OKFDDs
    IEEE International Conference on Computer Design, pp. 602-607, Austin, 1995


  79. drechsler96af
    Rolf Drechsler, Bernd Becker and Nicole G"ockel A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions
    International Conference on Artificial Neural Networks and Genetic Algorithms, pp. 392-395, Ales, 1995


  80. drechsler96ag
    Rolf Drechsler and Bernd Becker Sympathy: Fast Exact Minimization of Fixed Polarity Reed-Muller Expressions for Symmetric Functions
    IEEE European Design & Test Conference, pp. 91-97, Paris, 1995


  81. drechsler94
    Rolf Drechsler, Michael Theobald and Bernd Becker Fast OFDD based Minimization of Fixed Polarity Reed-Muller Expressions
    IEEE European Design Automation Conference, pp. 2-7, Grenoble, 1994


  82. drechsler97
    Rolf Drechsler and Nicole G"ockel
    Minimization of BDDs by Evolutionary Algorithms
    International Workshop on Logic Synthesis, Lake Tahoe, 1997


  83. drechsler97f
    Rolf Drechsler
    Secure Implementation of Decision Diagrams
    International Workshop on Logic Synthesis, Lake Tahoe, 1997


  84. drechsler97fg
    Rolf Drechsler
    Extensions of Decision Diagrams to the Word-Level
    Workshop on Post-Binary Ultra-Large Scale Integration, Santiago de Compostela, 1996
    E


    ECKER

  85. ecker88
    K. Ecker, D. Schutt,
    ``Testing of arrays of AND and EXOR functions,''
    J. Inf. Process. Cybern.
    (East Germany), vol.24, no.10, 521-7, 1988.

    EDWARDS

  86. edwards75
    C. R. Edwards,
    ``Novel digital integrated-circuit configurations based upon spectral techniques,''
    1st European Solid State Circuits Conference-ESSCIRC
    (Extended abstracts only), 82-3, x+130, 1975, IEE, London, England.

    EGGERSTEDT

  87. eggerstedt99
    M. Eggerstedt, N. Hendrich, and K. von der Heide,
    ``Minimization of Parity-Checked Fault-Secure AND/EXOR Networks,''
    Reed-Muller Proceedings
    , 1993.

    ELLIOT

  88. elliot-Rao82
    D. F. Elliot, K. R. Rao,
    ``Fast Transforms - Algorithms, Analyses, Applications''
    ,
    1982.
    F


    FALKOWSKI

  89. falkowski90
    B. J. Falkowski, and M. A. Perkowski,
    ``Algorithms for the Calculation of Hadamard-Walsh Spectrum for Completely and Incompletely Specified Boolean Functions,''
    Proc. of IEEE International Phoenix Conference on Computers and Communication,
    pp. 868 - 869, Scottsdale, Arizona, March 1990.

  90. falkowski90a
    B. J. Falkowski, and M. A. Perkowski,
    ``Essential Relations between Classical and Spectral Approaches to Analysis, Synthesis and Testing of Completely and
    Incompletely Specified Boolean Functions,'' Proc. of the IEEE ISCAS'90, International Symposium on Circuits and Systems,
    pp. 1656 - 1659, New Orleans, 1-3 May 1990.

  91. falkowski90b
    B. J. Falkowski, and M. A. Perkowski,
    ``A Family of All Essential Radix-2 Addition/Subtraction Multi-Polarity Transforms: Algorithms and Interpretations in Boolean Domain,''
    Proc. of the IEEE ISCAS'90, International Symposium on Circuits and Systems,
    pp. 2913 - 2916, New Orleans, 1-3 May 1990.

  92. falkowski90c
    B. J. Falkowski, and M. A. Perkowski,
    ``Algorithm and Architecture for Gray Code Ordered Fast Walsh Transform,''
    Proc. of the IEEE ISCAS'90, International Symposium on Circuits and Systems,
    pp. 1596 - 1599, New Orleans, 1-3 May 1990.

  93. falkowski90d
    B. J. Falkowski, and M. A. Perkowski,
    ``Walsh Type Transforms for Completely and Incompletely Specified Multiple-Valued Input Binary Functions,''
    Proc. of the 20th IEEE ISMVL, International Symposium on Multiple-Valued Logic,
    pp. 75 - 82, Charlotte, NC, May 1990.

  94. falkowski90e
    B. Falkowski, I. Schaefer, and M. Perkowski,
    ``A Fast Computer Algorithm for the Generation of Disjoint Cubes for Completely and Incompletely Specified Boolean Functions,''
    Proc. of the 33rd Midwest Symp. on Circuits and Systems,
    pp. 1119 - 1122, Alberta, Canada, August 1990.

  95. falkowski90f
    B. J. Falkowski, and M. A. Perkowski,
    ``One More Way to Calculate the Hadamard-Walsh Spectrum for Completely and Incompletely Specified Boolean Functions,''
    Int. J. Electron.
    , vol. 69, no.~ 5, pp. 595 - 602, November 1990.

  96. falkowski-perkowski91
    B. J. Falkowski, and M. A. Perkowski,
    ``On the Calculation of Generalized Reed-Muller Canonical Expansions from Disjoint Representation of Boolean Functions,''
    Proc. of the 33rd Midwest Symp. on Circuits and Systems,
    pp. 1131 - 1134, August 1990, Alberta, Canada. (Cat. No.90CH2819-1), vol.2, 1205, 1991, IEEE, New York, NY, USA.

  97. falkowski-perkowski91a
    B. J. Falkowski, and M. A. Perkowski,
    ``One more way to calculate generalized Reed-Muller expansions of Boolean functions,''
    Int. J. Electron.
    , vol. 71, no.3, 385-96, Sept. 1991.

  98. falkowski-perkowski91b
    B. J. Falkowski, and M. A. Perkowski,
    ``Algorithm for the Generation of Disjoint Cubes for Completely and Incompletely Specified Boolean Functions,''
    Int. J. Electron.
    , Vol. 70, No. 3, pp. 533 - 538, March 1991.

  99. falkowski91c
    B. Falkowski,
    ``Spectral Methods for Boolean and Multiple-Valued Input Logic Circuits,''
    Ph.D. Thesis,
    PSU, May 1991.

  100. falkowski92
    B. Falkowski, I. Schaefer, and M. Perkowski,
    ``Calculation of the Rademacher-Walsh Spectrum from a Reduced Representation of Boolean Functions,''
    Proc. of the IEEE EURO-DAC '92, European Design Automation Conference,
    pp. 181 - 186, Sept. 7-10, Hamburg, 1992.

  101. falkowski92a
    B. Falkowski, I. Schaefer, and M. Perkowski,
    ``Effective Computer Methods for the Calculation of Rademacher-Walsh Spectrum for Completely and Incompletely Specified Boolean Functions,''
    IEEE Trans. on Computer-Aided Design,
    pp. 1207 - 1226, October 1992.

  102. falkowski93
    B. Falkowski, I. Schaefer, and M. A. Perkowski,
    ``An Efficient Computer Algorithm for the Calculation of the Walsh Transform for Incompletely Specified Multiple-Valued Binary Functions,''
    Int. J. Electron.
    , vol. 75, no. 2., pp. 163-175, 1993.

    FEI

  103. fei-zhuang92
    B. Fei, and N. Zhuang,
    ``Fast logic synthesis based upon ternary universal logic module $U sub f$,''
    Proceedings. The Twenty-Second International Symposium on Multiple-Valued Logic,
    (Cat. No.92CH3113-8), 401-7, xv+482, 1992, IEEE Comput. Soc. Press, Los Alamitos, CA, USA.

  104. fei93
    B. Fei, Q. Hong, H. Wu, M. A. Perkowski, and N. Zhuang,
    ``Efficient Computation for Ternary Reed-Muller Expansions under Fixed-Polarities,''
    Int. J. Electron.
    , vol.~ 75, no.~ 4., pp. 685-688, 1993.

    FISHER

  105. fisher74
    L. T. Fisher,
    ``Unateness properties of AND-EXCLUSIVE-OR logic circuits,'' IEEE Trans. Comput.
    (USA), vol.C-23, no.2, 166-72, Feb. 1974.

    FLEISHER

  106. fleisher-tavel-yeager87
    H. Fleisher, M. Tavel, and J. Yeager,
    ``A computer algorithm for minimizing Reed-Muller canonical forms,''
    IEEE Trans. Comput.
    (USA), vol.C-36, no.2, 247-50, Feb. 1987.

    FRALEIGH

  107. fraleigh89
    J. B. Fraleigh,
    A First Course in Abstract Algebra
    , Section 7.2, 4th ed. Addison Wesley Publishing Company, Inc., 1989.

    FRIEDMAN

  108. FRIE87
    S. J. Friedman, and K. J. Supowit,
    ``Finding the Optimal Variable Ordering for Binary Decision Diagrams,''
    Proc. 24th ACM/IEEE DAC
    , pp. 348-356, 1987.

    FROESSL

  109. froessl-eschermann91
    J. Froessl, and B. Eschermann,
    ``Module generation for AND/XOR-fields (XPLAs),''
    IEEE International Conference on Computer Design: VLSI in Computers and Processors,
    (Cat. No.91CH3040-3), 26-9, xvi+654, 1991, IEEE Comput. Soc. Press, Los Alamitos, CA, USA.

    FUIJTA

  110. fujita
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    WWWWW



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    WU

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    YAMADA

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