CURRICULUM VITAE
W. Robert Daasch
Department of Electrical and Computer Engineering
Maseeh College of Engineering and Computer Science
Portland State University
PO BOX 751 - ECE
Portland, OR 97207
1 January 2017 Education

Academic Employment and Appointments

Emeritus Professor, Electrical and Computer Engineering, Portland State University, Portland, OR, December 2016–present (original appointment, Assistant Professor, Electrical and Computer Engineering, November 1986)

Professor, Director Integrated Circuits Design and Test Laboratory, Electrical and Computer Engineering, Portland State University, Portland, OR, August 2003–2016 (original appointment, Assistant Professor, Electrical and Computer Engineering, November 1986)

Associate Professor, Electrical and Computer Engineering, Portland State University, Portland, OR, September 1992–2003

Member of the Oregon State University Graduate Faculty, Electrical and Computer Engineering, Corvallis, OR, January 1999–2004

Adjunct Assistant Professor, Biomedical Information Communication Center, Oregon Health Sciences University, Portland, OR, 1989-1990

Assistant Professor, Electrical Engineering, Portland State University, Portland, OR, November 1986–1992

Assistant Professor, visiting, Electrical and Computer Engineering, Illinois Institute of Technology, August 1984–December 1986

Systems Analyst, University of Washington/Northwest VLSI Consortium, Department of Computer Science, University of Washington, December 1982–August 1984

Organic Laboratory Instructor, Department of Chemistry, University of Washington, March 1982–November 1982 Dissertation Requirements of L2 Wavefunctions for Core Ionization and Molecular Properties

Professor E. R. Davidson, Department of Chemistry, University of Washington, Supervisor Summary

The dependence of the ionization profile on the number and type of functions used to describe the electrons in a molecular system was analyzed using the moments of the calculated orbital energy distribution. All calculations used a Hartree-Fock approximation to the atomic and molecular Hamiltonians. In addition, as the number of electrons in the system increases it becomes attractive to model core electrons as a point charge at the nucleus. In doing so however, molecular properties that depend on core electrons cannot be evaluated as before. In the second part of my dissertation, I presented a new technique that uses the point charge model for the core electrons that is shown by comparison to experimental results to predict reliable values for these molecular properties. Refereed Publications and Other Reviewed Achievements Articles

Cumulative Total 1986-present: 17.

C.G. Shirley, W.R. Daasch, “Copula Models of Correlation: A DRAM Case Study,” IEEE Transactions on Computers, vol.63, no.10, pp.2389,2401, Oct. 2014

W.R. Daasch, C.G. Shirley, A. Nahar, “Statistics in Semiconductor Test: Going beyond Yield,” IEEE Design & Test of Computers, pp. 64-73 Sept. 2009

K.M. Butler, J.M. Carulli, J. Saxena, A. Nahar, W.R. Daasch, “Multidimensional Test Escape Rate Modeling,” IEEE Design & Test of Computers, pp. 74-82 Sept. 2009

R. Turakhia, R. Daasch, J. Lurkins, B. Benware, “Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers”, IEEE Design & Test of Computers, pp. 100-109, February 2006

R. Madge, B.R. Benware, R. Daasch, “Obtaining High Defect Coverage for Frequency Dependent Defects on Complex ASICs,” IEEE Design and Test of Computers, pp. 46-53, Sept-Oct 2003

C-H Lim, W.R. Daasch, G. Cai, “Design of CMOS VLSI Circuits under Thermal Constraint”, IEEE Transactions on Circuits and Systems, Vol. 49, No 8, pp. 589-593, Aug 2002

K. Cota, W.R. Daasch, R. Madge, J. McNames, “Neighborhood selection for @I sub DDQ@ outlier screening at wafer sort”, IEEE Design and Test of Computers, Vol. 19 No. 5, pp. 74-81, Sept-Oct 2002

W.R. Daasch, C.F. Hawkins, A. Keshavarzi, S. Narendra, K. Roy, M. Sachdev, J.W. Tschanz, De Vivek, “Leakage and process variation effects in current testing on future CMOS circuits”, IEEE Design and Test of Computers, Vol. 19 No. 5, pp. 36-43, Sept-Oct 2002

A. Dhodapkar, C-H Lim, G. Cai, W.R. Daasch, “TEM2P2EST: A Thermal Enabled Multi-Model Power/Performance Estimator”, Lecture Notes on Computer Science, PACS 2000, First International Workshop on Power-Aware Microarchitectural/Circuit Techniques, Lecture Notes in Computer Science, Vol. 2008, pp. 112-125, Springer-Verlag, Heidelberg, Germany, 2001

D.H-C. Chiang, R. Schaumann, W.R. Daasch, “Simulation and Measurement of Fully-differential CMOS OTAs,” Frequenz, Vol. 51, pp. 85-94, 1997

M.A. Driscoll, W.R. Daasch, “Accurate Predictions of Parallel Program Execution Time,” Journal of Parallel and Distributed Computing, Vol. 25, pp. 16-30, Feb 1995

M.A. Driscoll, W.R. Daasch, and C Sembakutti, “Efficient Design Centering of Analog Integrated Circuits Using Binary Search,” Analog Integrated Circuits and Signal Processing, vol. 6(2), pp. 157-169, Sept 1994

W.R. Daasch, M. Wedlake, R. Schaumann, “Automatic Generation of CMOS Continuous-Time Elliptic Filters”, Electronics Letters, Vol. 28, pp. 2215-2216, Nov 1992

R. Schaumann, W.R. Daasch, “Design and Design Automation of Continuous-Time Fully Integrated Transconductance-C Filters”, Frequenz, Vol. 46, pp. 117-123, Apr 1992

W.R. Daasch, M. Wedlake, R. Schaumann, P. Wu, “Automation of the IC layout of continuous-time transconductance-C filters,” invited, International Journal on Circuit Theory and Applications, Vol. 20, pp. 267-282, May-June 1992

W.R. Daasch, “An Inexact Associative Memory Cell,” Electronics Letters, Vol. 27(18), pp. 1623-1625, Aug 1991

W.R. Daasch, S. Werden, D. Feller, E.R. Davidson, “Can any information about reaction paths be obtained from the reduced mass?,” J. of Molecular Structure, Vol. 103, pp 177-181, 1983

W.R. Daasch, E.R. Davidson, A.U. Hazi, “Oxygen K hole photoionization cross section of @CO sub 2@,” J. Chem. Phys., Vol. 76(12), pp. 6031-6036, 1982

W.R. Daasch, L.E. McMurchie, E.R. Davidson, “Molecular properties from pseudo-wavefunctions,” Chem. Phys. Let., Vol. 84(1), pp. 9-12, 1981

L.B Knight, M.B. Wise, A.G. Childers, E.R. Davidson, W.R. Daasch, “Codeposition generation of BeCl in an argon matrix at 12K, An ESR investigation,” J. Chem. Phys., Vol. 74(8), pp 4256-4260, 1981

L.B. Knight, M.B Wise, A.G. Childers, E.R. Davidson, W.R. Daasch, “The generation and ESR investigation of the BeF radical in rare gas matrices,” J. Chem. Phys., Vol. 73(9), pp. 4198-4202, 1980

R.L. Martin, W.R. Daasch, and E.R. Davidson, “An L2 calculation of the 1s and 2s photoionization- cross sections of Ne,” J. Chem. Phys., Vol 71(6), pp. 2375-2380, 1979 Patents

Cumulative Total 1986-present: 4.

Inventors: C.G. Shirley, W.R. Daasch, Copula-based system and method for management of manufacturing test and product specification throughout the product life-cycle for electronic systems or integrated circuits, 9,052,358, June 9, 2015 Inventors: H. Xiao, R. Schaumann, W.R. Daasch “High-frequency active inductor” United States Patent No. 7,042,317, May 9, 2006

Inventors: R. Madge, E. Sugasawara, W.R. Daasch, J.N. McNames, D.R. Bockelman, K. Cota, “Test Limits Based on Position”, United States Patent No. 6,598,194, July 22, 2003

Inventors: R. Madge, E. Sugasawara, W.R. Daasch, J. McNames, D. Bockelman, K. Cota, “Statistical Decision System”, United States Patent No 6,782,500, August 24, 2004 Conference Publications or Other Creative Achievements Conference Papers, Technical Reports, Poster Sessions

Cumulative Total 1986-present: 52.

K. Butler, A. Nahar, R. Daasch, “What We Know After Twelve Years Developing and Deploying Test Data Analytics,”, IEEE International Test Conference, p 8.2, Dallas-Fort Worth, TX, Nov 2016

S.Siatkowski, C. Shan, Li-C Wang, N. Sumikawa, W.R. Daasch, J.M. Carulli, “Consistency in Wafer Based Outlier Screening”, IEEE VLSI Test Symposium, pp. 1-6, Las Vegas NV, April 2016, Awarded IEEE VLSI Test Symposium Best Paper 2016

S.Siatkowski, C. Shan, Li-C Wang, N. Sumikawa, L. Wineberg, W.R. Daasch, “Generalization Of An Outlier Model Into A ¿Global¿ Perspective”, IEEE International Test Conference, pp 1-10, Anaheim, CA, Oct 2015

C.G. Shirley, W.R Daasch, P. Nigh, Z. Conroy, “Board Manufacturing Test Correlation to IC Manufacturing Test”, International Test Conference, Seattle, WA, Oct. 2014

Y-S Wang, W.R. Daasch, “Copula-based Technique to Identify Miscorrelating Outlier between Test and UseU, poster session, International Test Conference, Seattle, WA, Oct. 2014.

W.R Daasch, “Requirements for End-to-End Data Collection”, Industrial Test Challenges Workshop, International Test Conference, Seattle, WA, Oct. 2014.

W.R Daasch, Z. Conroy, “End-to-End Analysis of Customer Failures”, Industrial Test Challenges Workshop, International Test Conference, Anaheim, CA, Oct 2013.

K.R. Gotkhindikar and W.R. Daasch, K.M. Butler, J.M. Carulli Jr. and A. Nahar, “Die-level Adaptive Test: Real-time Test Reordering and Elimination,” International Test Conference, Anaheim, CA, Sept 2011.

W.R. Daasch, “Naturally Occurring Data Statistical Test Diagnosis,” Industrial Test Challenges, Austin, TX, November 2010.

W.R. Daasch, “Adaptive Test Flows, Is the naturally occurring test data enough?,” Data Driven Test Workshop, Industrial Test Challenges Workshop, in association with the International Test Conference, Austin, TX, November 2010.

W.R. Daasch, “Directions for Statistical Test (Less testing more information),” invited Plenary Speaker at the Workshop for Design Manufacturability and Reliability, in association with the Design Automation Conference, Anaheim CA, June 2010.

N. Velamati, W.R. Daasch, “Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering,” VLSI Test Symposium, June 2009, Santa Cruz, CA

R. Gudavalli, W.R. Daasch P. Nigh, D. Heaberlin, “Application of non-parametric statistics of the parametric response for defect diagnosis,” IEEE International Test Conference, Nov. 2009 Austin, TX

W. Robert Daasch, “Outliers and the Testing Tools that Reveal Them: A Fair and Balanced Introduction to Statistics in Test”, IEEE International Test Conference, invited embedded tutorial, Oct. 2008.

W.R. Daasch, S. Jain, D. Armbrust, “Analyzing the Impact of Fault-tolerant BIST for VLSI Design,” IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp. 152-160, October 2008

R. Turakhia, Mark Ward, W.R Daasch Reducing the Cost of Test - an Adaptive Test Solution IEEE Test Synthesis Workshop, May 2008

Turakhia, R., Daasch, W.R., Ward, M., Van Slyke, J., “Silicon evaluation of longest path avoidance testing for small delay defects” IEEE International Test Conference, Paper 8E-3, Santa Clara CA, October 2007

W.R. Daasch, D. Armbrust, Using Fault Tolerant Methods in DFT Circuitry IEEE Test Synthesis Workshop, May 2007

W.R. Daasch, “It’s Not What You Can MakeýIt’s What You Can Test”, IEEE International Test Conference, p. 15 October 2006.

K. Butler, S. Subramaniam, A. Nahar, J Carulli, T. Anderson, W.R Daasch, “Successful Development and Implementation of Statistical Outlier Techniques on 90nm and 65nm Process Driver Devices”, IEEE International Reliability Physics Symposium, Paper 5E-3, San Jose CA, March 2006

A. Nahar, R. Daasch, S. Subramaniam, “Burn-in Reduction Using Principal Component Analysis”, Proceedings International Test Conference, Nov. 2005

R. Daasch, R. Madge, “Data-Driven Models for Statistical Testing: Measurements, Estimates and Residuals”, Proceedings International Test Conference, Nov. 2005

B. Benware, R. Madge, M. Ward, R. Daasch, ”The Value of Statistical Testing for Quality, Yield and Test Cost Improvement” Proceedings International Test Conference, Nov. 2005

R. Daasch, R. Madge, “Variance Reduction and Outliers: Statistical Analysis of Semiconductor Test Data”, Proceedings International Test Conference, Nov. 2005

L. Ning, A. Nahar, R. Daasch, K.M. Butler, J.M. Carulli, S. Subramaniam, “Burn-in Reduction using Robust Canonical Correlation Analysis”, Semiconductor Research Corporation TECHCON 2005, Portland, OR, Oct. 2005

R. Daasch, “Improving Outlier Screening,” Semiconductor Research Corporation CADTS Test and Testability Review, Atlanta, GA, May 2005

R.Turakhia, T. Shannon, R. Daasch, B. Benware, B. Madge, “Defect Screening Using Independent Component Analysis on IDDQ”, IEEE VLSI Test Symposium, April 2005

X. Haiqiao, R. Schaumann, W.R. Daasch, P.K. Wong, B. Pejcinovic, “A radio-frequency CMOS active inductor and its application in designing high-Q filters”, Proceedings International Symposium on Circuits and Systems pp. 197-200, May 2004

C. Schuermyer, J. Ruffler, R. Daasch, R. Madge, “Minimum testing requirements to screen temperature dependent defects”, Proceedings International Test Conference, pp. 300-308, Oct. 2004 2004, Awarded IEEE International Test Conference Honorable Mention 2004

R. Madge, B. Benware, R. Turakhia, R. Daasch, C. Schuermyer, J. Ruffler, “In search of the optimum test set-adaptive test methods for maximum defect coverage and lowest test cost”, Proceedings International Test Conference, pp. 203-212, Oct. 2004

R. Daasch, M. Rehani, “Dude! where’s my data? - cracking open the hermetically sealed tester”, Proceedings International Test Conference, 2004, panel session, p. 1428, Oct 2004

E. Long, W.R. Daasch, R. Madge, B. Benware, “Detection of temperature sensitive defects using ZTC,” IEEE VLSI Test Symposium, pp. 185-190, April 2004

C. Schuermyer, B. Benware, K. Cota, R. Madge, R. Daasch, L Ning, “Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ,” International Test Conference, pp. 565-573, Charlotte, NC, Oct 2003

B. Benware, R. Madge, C. Lu, R. Daasch, “Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs,” VLSI Test Symposium, pp. 39-46, Napa, CA, May 2003, Awarded IEEE VLSI Test Symposium Best Paper 2003,

W.R. Daasch, “Parametric Variation or Defects? Statistical Post-Processing Analysis of Wafer-Sort Data”, International Symposium for Testing and Failure Analysis, pp. 302-307, Phoenix, AZ, Nov 2002

R. Madge, B. Goh, V. Rajagopaian, C. Macchietto, C. Schuermyer, C. Taylor, D. Turner and W.R. Daasch “Screening @MinV sub DD@ outliers using Feed-Forward @V sub DD@ testing and @DELTA V sub DD@ Statistical Post-Processing”, IEEE International Test Conference, pp. 673-682, Baltimore, MD, Oct 2002

D. Turner, J.N. McNames, D. Abercrombie, W.R. Daasch and R. Madge, “Isolating and Removing Sources of Variation in Test Data”, IEEE International Test Conference, pp. 464-471, Baltimore, MD, Oct 2002

R. Madge, M. Rehani, K. Cota, R. Daasch, “Statistical Post-Processing at Wafer-sort – An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies,” IEEE VLSI Test Symposium, pp. 69-74, Monterey, CA, Apr 2002

C-H Lim, W.R. Daasch, G. Cai “Thermal Scheduling for Ultra-low power Mobile Microprocessor,” Workshop on Complexity-effective Design, Anchorage, AK, May 2002

C-H Lim, W.R. Daasch, G. Cai “A Thermal Aware Superscaler Microprocessor,” IEEE Symposium on Quality Electronic Design, pp. 517-523, San Jose, CA, Mar 2002

W.R. Daasch, J.N. McNames, K. Cota, and R. Madge “Neighbor Selection for Variance Reduction in @size 14 { I sub DDQ } @ and Other Parametric Data”, IEEE International Test Conference, pp. 92-100, Baltimore, MD, Oct 2001, Awarded IEEE International Test Conference Best Paper 2001

W.R. Daasch, J.N. McNames, D. Bockelman, K. Cota, and R. Madge “Variance Reduction Using Wafer Patterns in @size 14 { I sub DDQ } @ Data”, IEEE International Test Conference, pp. 189-198, Atlantic City, NJ, Oct 2000

K. Lofstrom, W.R. Daasch, and D. Taylor, “IC Identification Circuit using Device Mismatch,” IEEE International Solid-State Circuit Conference, pp. 372-373, San Francisco, CA, Feb 2000

C-H Lim, and W.R. Daasch, “Output Buffer with Self-Adjusting Slew Rate and On-Chip Compensation,” IEEE Symposium on IC/Package Design Integration, pp. 51-55, Santa Cruz, CA, Feb 1998

D.H-C. Chiang, R. Schaumann, and W.R. Daasch, “Test Board Design and Measurement Techniques for High-Frequency Fully-Differential CMOS OTAS,” IEEE International ASIC Conference and Exhibit, pp. 321-326, Portland, OR, Sept 1997

W.R. Daasch and J. Lee, “A Word/Bit Parallel Inexact Match Content Addressable Memory,” Seventh IEEE International ASIC Conference and Exhibit, pp. 25-28, Rochester, NY, Sept 1994

P. Wu, R. Schaumann, W.R. Daasch, “A 20 MHz fully-balanced transconductance-C filter in 2 micron CMOS technology,” IEEE International Symposium on Circuits and Systems, pp. 1188-1191, Chicago, IL, May 1993

A. Sarabi, P. Ho, K. Iravani, W.R. Daasch, and M. Perkowski, “Minimal Multi-level Realization of Switching Functions Based on Kronecker Functional Decision Diagrams”, 1993 Workshop on Multi-level Logic Synthesis, Lake Tahoe, NV, May 1993

W.R. Daasch and M. Wedlake, “Rapid Layout of a Continuous-Time Transconductance-C Filter,” IEEE International Symposium on Circuits and Systems, pp. 2256-2259, San Diego, CA, 1992

L. Schaefer, W.R. Daasch and M.A. Driscoll, “Parallelization of Engineering Software in a Distributed System”, Poster Session, Oregon ASTI Executive Conference, Eugene, OR, Apr 1991

J. Jia, and W.R. Daasch, “A Voltage Controlled Resistance for MOS Transistors”, invited lecture session, SPOCAD IV, Seattle, WA, Aug 1988

W.A. Payne III, F. Makedon, and W.R. Daasch, “High Speed Interconnection Using the Clos Network,” Proceedings of the 1st International Conference on Supercomputing, pp. 96-111 Athens, Greece, June 1987

W.R. Daasch and R. Fowler, “A Netlist/Presim/Rnl Tutorial,” Technical Report 84-07-01, Department of Computer Science, University of Washington, Seattle, WA, July 1984

W.R. Daasch, “Evaluation of Effective Resistances for MOS Transistors,” Technical Report, DARPA Contractors Meeting, University of North Carolina, Chapel Hill, NC, November 1983 Teaching Achievements New Courses

ECE 575, Graduate course title “Introduction to Integrated Circuit Testing”, First taught 1999 as EE 510(ATE), “Design and Use of Automatic Test Equipment for Integrated Circuit Design”, funded by OUS SB 504 Engineering Education Initiative

ECE 525/526/527 ECE 627 and ECE 425/426. Graduate and Senior courses in custom VLSI design, Portland State University. Taught annually since 1987

EE 589 (was EE 510LN, Spring 1991), Graduate Course Performance Analysis of Local Area Networks

EE 50x, Research, Thesis, Reading and Conference, Special Projects, Cooperative Education/Internship, 300+ credits accumulated since 1987

EE 60x, Research, Dissertation, Reading and Conference, Special Projects, Cooperative Education/Internship, 100+ credits accumulated since 1987 Undergraduate Students Advised

Undergraduate Advisor to an average of 15 Electrical and Computer Engineering students (Junior/Senior) per year 1988-2000. Undergraduate advising was reorganized to have a single advisor for all ECE majors. Graduate Students Advised

Graduate Advisor to an average of 10 per year 1988-2000 Electrical and Computer Engineering graduate students Doctoral, M.S. thesis, and M.S. non-thesis levels. Graduate advising was reorganized to have a single advisor for all admitted graduate students. Since 2000, faculty graduate was reduced to thesis students. Current thesis and dissertation students

Cumulative total 19860-present: PhD 2, MS ECE Thesis 37.

Yu-Shan Wang, PhD candidate;

Chris Cowan, PhD pre-candiate

Significant Professional Development Activities Service to Community Outside Seminars and Tutorials

W.R. Daasch, “Naturally Occurring Data Statistical Test Diagnosis,” Industrial Test Challenges, Austin, TX, November 2010.

W.R. Daasch, “Adaptive Test Flows, Is the naturally occurring test data enough?,” Data Driven Test Workshop, in association with the International Test Conference, Austin, TX, November 2010.

W.R. Daasch, “Directions for Statistical Test (Less testing more information),” invited Plenary Speaker at the Workshop for Design Manufacturability and Reliability, in association with the Design Automation Conference, Anaheim CA, June 2010.

W.R. Daasch, “Outliers and the Testing Tools that Reveal Them: A Fair and Balanced Introduction to Statistics in Test”, W. Robert Daasch, IEEE International Test Conference, invited embedded tutorial, Oct. 2008.

Invited Plenary Paper: W.R. Daasch, “It’s Not What You Can Make It’s What You Can Test”, IEEE International Test Conference, p. 15, invited plenary speaker, October 2006.

W.R. Daasch, “Parametric Variation or Defects? Statistical Post-Processing Analysis of Wafer-Sort Data”, Electronic Device Failure Analysis Society International Symposium for Testing and Failure Analysis, pp., Nov 2002, Phoenix, AZ

W.R. Daasch, “Outlier Screening of IC Test Data: From Test Response to Test Information,” 1/2 day tutorial presented at North Atlantic Test Workshop, Burlington, VT, May 2005

W.R. Daasch, “Die Products Consortium: Role in PSU Research,” Defects Products Consortium, May 2005

W.R. Daasch, “Statistical Post-Processing of IC Test Data,” 1/2 day tutorial presented at Texas Instruments, Dallas, TX, Oct 2003

W.R. Daasch, “Transition Delay Faults and Statistical Post-Processing”, presented jointly with C. Macchietto, R. Madge LSI Logic, Gresham OR, Defects Products Consortium, Baltimore, MD, Oct 2002

W.R. Daasch, “Statistical Post-Processing”, presented jointly with R. Madge LSI Logic, Gresham OR, Industrial Test Challenges, Intel Corporation, Santa Clara, CA, May 2002

W.R. Daasch, “High-Frequency, High-Q, Self-Correcting Integrated Analog Filters”, SRC Contractors Research Review, jointly presented A. Karsilayan Texas A&M University, University of Washington, Seattle, WA, Aug 2001

W.R. Daasch, “Yield Loss or Revenue, Statistical Post-Processing of Wafer Sort Test Data”, presented jointly with R. Madge LSI Logic, Gresham, OR, Industrial Test Challenges, University of Southern California, Los Angeles, CA, May 2001

W.R. Daasch, “IC Identification using Transistor Mismatch”, IBM Microelectronics, Test Resources Working Group, Burlington, VT, June 2000

W.R. Daasch, “Outlier Screens at Wafer Sort”, Industrial Test Challenges, IBM Microelectronics, Burlington, VT, May 2000

W.R. Daasch, “A New Average IC Power Analysis Method”, Simulation and Test Group, Mentor Graphics Corp, Aug 1997

W.R. Daasch, “A New Cycle Based IC Power Analysis Method”, Simulation and Test Group, Mentor Graphics Corp, July 1997

W.R. Daasch, “IC Power Analysis Research Review”, Simulation and Test Group, Mentor Graphics Corp, January 1997

W.R. Daasch, “Switch Level Simulation”, Digital Controls Group, Bonneville Power Administration, Oct 1991 Consulting

Jones Day, Chicago IL, intellectual property consultant, 2009-2011

IC Designs, Lynnwood, WA, for the design and implementation of CAE integrated circuit design software for personal computers, 1984-1987

Advanced Inquiry System, Hillsboro, OR. Member of the corporations technical advisory board, 2007-2010. Service to University, College, Department

Portland State University Faculty Senate Educational Policy Committee, 2013-2016

Portland State University Article 18 Review Committee, Co-chair, Fall 2014.

Portland State University Faculty Senate Steering Committee, 2009-2014

Portland State University Faculty Senate Presiding Officer, 2012-2013, elect 2011-2012, past 2013-2014

Portland State University Faculty Senate, 2009-2013

Portland State University Faculty Senate, 2000-2003

Portland State University Faculty Senate Budget Committee, 2001-2004

Portland State University Faculty Senate Steering Committee, 1997-1998

Portland State University Faculty Senate Committee on Committees, 1995-1997

Portland State University Faculty Senate, 1995-1998

Campus Academic Computing Advisory Committee member, Portland State University, 1995-97, chair 1996-97

Campus Academic Computing Advisory Committee member, Portland State University, 1989-92, chair 1992-93

College of Engineering and Computer Science, Curriculum Committee, 2001-2004

Electrical and Computer Engineering Departmental Charter Committee, e.g. Promotion and Tenure (chair 4 times), Curriculum, Computing, Graduate Affairs, 1987-present

Electrical Engineering Department Faculty Secretary, 1992-1995

Ad-Hoc Committee for the Design of a Campus Computer Network, Portland State University, 1990

Undergraduate Advisor, 1988-89

Electrical Engineering System Science Representative, 1988-89

Department of Computer Science Faculty Search Committee Member, 1988-89 1993-1994, 2005-2006. Service to Profession

Member Program Committee 2002 Defects Based Test Workshop, Monterey, CA, May 2002

IEEE 1997 International ASIC Conference and Exhibit, Workshop and Tutorial Chairman, Portland, OR, September, 1997

Member Technical Activities Committee, IEEE ASIC Conference, 1997-1999

IEEE International Symposium on Circuits and Systems, Publicity Chairman, Portland, OR, June, 1989

Fundamentals of Engineering Review Course, Chemistry section, Portland State University, 1989, 1990 Research or Other Creative Works in Progress

Token Drafting in Self-Timed Integrated Circuits, W. Robert Daasch, Chris Cowan, PhD project in collaboration with Dr. Ivan Sutherland and the Asynchronous Research Center.

Test and Use Yield Modeling of Analog Circuits, W. Robert Daasch, YuShan Wang, PhD project in collaboration with the Integrated Circuits Design and Test Laboratory Honors, Grants, Donations and Fellowships Honors

Awarded IEEE VLSI Test Symposium Best Paper 2016: S.Siatkowski, C. Shan, Li-C Wang, N. Sumikawa, W.R. Daasch, J.M. Carulli, “Consistency in Wafer Based Outlier Screening”, IEEE VLSI Test Symposium, pp. 1-6, Las Vegas NV, April 2016,

Sigma Xi Outstanding Engineering Researcher, Columbia-Willamette Chapter, 2009

Awarded 2008 GRC Technical Excellence in Research, Semiconductor Research Corporation, November 2008.

Awarded IEEE International Test Conference Outstanding Lecture Series: R. Daasch, R. Madge, “Production Data-Driven Statistical Testing”, November 2005, IEEE International Test Conference, Austin TX

Awarded IEEE International Test Conference Honorable Mention Paper 2004: C. Schuermyer, J. Ruffler, R. Daasch, R. Madge, “Minimum testing requirements to screen temperature dependent defects”, Proceedings International Test Conference, pp. 300-308, Oct. 2004 IEEE International Test Conference, Charlotte NC

Awarded IEEE VLSI Test Symposium Best Paper 2003: B. Benware, R. Madge, C. Lu, R. Daasch, “Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs,” VLSI Test Symposium, pp. 39-46, Napa, CA, May 2003

Awarded IEEE International Test Conference Best Paper 2001: W.R. Daasch, J.N. McNames, K. Cota, and R. Madge “Neighbor Selection for Variance Reduction in @size 14 { I sub DDQ } @ and Other Parametric Data”, IEEE International Test Conference, pp. 92-100, Baltimore, MD, Oct 2001 Grants Awarded

Cumulative total 1990-present: $3.2 million.

Systematic Statistical Outlier Screening, PI Semiconductor Research Corporation, Principal Investigator $165,000, 2013-2016.

“Statistical Modeling of Device Manufacturing, Test and Use,” Semiconductor Research Corporation, Principal Investigator W.R. Daasch, $300,000, 2010-2012

“Virtual Integrated Device Manufacturing,” Cisco Systems, Principal Investigator W.R. Daasch, PSU Foundation award, $100,000, 2012.

“Virtual Integrated Device Manufacturing,” Cisco Systems, Principal Investigator W.R. Daasch, PSU Foundation award, $100,000, 2010.

“Aligning System and Component Testing for Improved Product Quality,” Cisco Systems, Principal Investigator W.R. Daasch, PSU Foundation award, $41,000, 2009.

“Testing Embedded DRAM in ASICs”, LSI Logic Corporation, Principal Investigator W.R. Daasch, $50,000, 2009

“Screening for Systematic Defects and Design for Manufacturability” LSI, Principal Investigator W.R. Daasch, $41,500, 2008

“Gold Aluminum Contact Assessment, a Novel Application to Semiconductor Test III”, Octavian Scientific and Oregon University System Oregon Metals Initiative, Principal Investigator W.R. Daasch, $16,000 2008

“Stochastic Modeling of Device Test Input, Test Flow, and Test Response” Semiconductor Research Corporation, Principal Investigator W.R. Daasch, $334,000, 2007-2010

“Statistical Screening of Semiconductor Test Data for Improved SPQL”, IBM Corporation Principal Investigator W.R. Daasch, $60,000 2006-2007

“Gold Aluminum Contact Assessment, a Novel Application to Semiconductor Test II”, Octavian Scientific and Oregon University System Oregon Metals Initiative, Principal Investigator W.R. Daasch, $70,000 2007

“Test Effectiveness Wafer-Sort and Final Test Defect Screening and Adaptive Test, Year 2” LSI Logic, Principal Investigator W.R. Daasch, $81,500, 2006

“Gold Aluminum Contact Assessment, a Novel Application to Semiconductor Test”, Octavian Scientific and Oregon University System Oregon Metals Initiative, Principal Investigator W.R. Daasch, $49,989, 2006

“Test Effectiveness Wafer-Sort and Final Test Defect Screening and Adaptive Test” Principal Investigator W.R. Daasch, J.N. McNames, $163,000, 2005

“Outlier Screening for Reduced Burn-In,” Semiconductor Research Corporation, Principal Investigator W.R. Daasch, $168,000, 2004-2007

“Full-wafer Wafer Contact”, Octavian Scientific, Principal Investigator W.R. Daasch, $34,331, 2004

“Defect Screening for Deep-Submicron Technology II”, LSI Logic Corporation, Principal Investigators J.N. McNames and W.R. Daasch, $162,000, 2004

“Defect Screening for Deep-Submicron Technology II”, LSI Logic Corporation, Principal Investigators J.N. McNames and W.R. Daasch, $162,000, 2003

“Full-wafer Wafer Contact”, Octavian Scientific, Principal Investigator W.R. Daasch, $20,515, 2003

“Defect Screening for Deep-Submicron Technology”, LSI Logic Corporation, Principal Investigators W.R. Daasch and J.N. McNames, $149,000, 2002

“Statistical Identification of Sources of Variation in Wafer E-Test Data”, LSI Logic Corporation, Principal Investigators W.R. Daasch and J.N. McNames, $75,000, 2001

“Next Generation @I sub DDQ@ Testing”, LSI Logic Corporation, Principal Investigators W.R. Daasch and J.N. McNames, $50,000, 2000

“High-Frequency, High-Q, Self-Correcting Integrated Analog Filters”, Semiconductor Research Corporation, Principal Investigators W.R. Daasch and R. Schaumann, $342,000, 2000-2002

“Electromagnetics Theory and Practice in Junior Level Courses” Intel and Oregon University System, Principal Investigators B. Pejcinovic, L. Casperson, and R. Daasch, $44,000, 2000-2001

“Oregon Joint Electronics Education Program,” Intel and Oregon University System, Principal Investigator, W.R. Daasch, and S-L. Liu (ECE Oregon State University), $75,000, 1999

“Robotics Laboratories for ECE Undergraduates,” Intel and Oregon University System, Principal Investigator, W.R. Daasch, M. Perkowski, and A. Mishchenko, $45,000, 1999

“Automatic Test Equipment Design and Use,”, Oregon University System, SB 504 Engineering Education Initiative, Principal Investigator, W.R. Daasch, $20,000, 1998

“CAE Tools for Low-Power IC Design,”, Mentor Graphics Corporation, Principal Investigator, W.R. Daasch, $34,144, 1996

“Network-Based Training and Access to HPC using NERO” -- the Network for Engineering and Research in Oregon, National Science Foundation, Investigators, W.R. Daasch, and M.A. Driscoll, $186,000.00. The $186,000 is the PSU subcontract of a $1.3 million grant to the Oregon Joint Graduate Schools of Engineering, Principal Investigators, C. Pancake (OSU), M. Landau (OSU) and A. Malony (UO), 1995-1998

“Design Automation of Continuous-Time Transconductance-C Filters,” Rapid Prototyping and Fabrication Program, National Science Foundation, Principal Investigator, W.R. Daasch, Co-principal investigator, Rolf Schaumann, $239,000.00, 1992-1995

“Graduate Assistantship for the Design of Content Addressable Memories”, Principal Investigator, W.R. Daasch, In-Focus Systems, $10,000, 1991

“Parallelization of Scientific Software”, Argonne Supercomputer Center, Principal Investigator, W.R. Daasch, Internet accounts for system configurations, 26 processor S81 Sequent, 40 node Sun network, Intel IPSC/2, not available in Oregon

“Parallel Design Centering on Shared Memory Multiprocessors”, Portland State University, Faculty Development 1990, $7,500, Co-principal Investigator, M. Driscoll

“Parallel Design Centering on Shared Memory Multiprocessors”, Portland State University, Research and Publications 1990, $1,000

1987-99 MOSIS Introductory and Advanced education in integrated circuit design fabrication budget $150,000, multiple awards for the period listed Donations

Cumulative total 1990-present: hardware $ 3.4 million, software $1.5 million.

“A Request for RF and Mixed Signal Automatic Test Equipment to Credence Systems Corporation,” Credence Systems Corporation, Beaverton, OR, $2,049,000, 2001

“A Request for 200mm Wafer-probe and Temperature Control to Electroglas Incorporated,” Electroglas Incorporated, San Jose, CA, $249,000, 2001

“A Request for Test Development System to TSSI Inc,” TSSI Inc, Beaverton, OR, $100,000, 1999

“A Request for Automatic Test Equipment to Credence Systems Corporation,” Credence Systems Corporation, Beaverton, OR, $1,020,000, 1998

“A Request for Visual HDL and Visual TestBench to Summit Design Inc,” Summit Design Inc, Beaverton, OR, $1,000,000, 1997

“Muiti-media in the Classroom, Phaser 350”, Tektronix Inc, Beaverton, OR, $5,495, 1997

“Muiti-media in the Classroom”, Lightware Inc, Beaverton, OR $6,500, 1996

Analogy Inc, Beaverton, OR, Saber simulator and analyzer for mixed-mode, digital, analog circuit design and analysis, Versions 3.1, 4.1, (4.2 4.3 upgrade), Total value approximately $300,000, 1991, 1996 (1997, 1998)

Phase Three Logic, Beaverton, OR, $11,000.00, CapFast Computer Aided Engineering Software for circuit schematic capture, 1990

Tektronix Inc, Beaverton, OR, $9,400.00, 67% School of Engineering and Science cost sharing for 7 Model 4319 UTek/X Workstations with 300 Mbyte HD, 16 Mbyte RAM, 19" Color Monitor, 1990

Tektronix Inc, Beaverton, OR, $7,996.00, 80% School of Engineering and Science cost sharing for SGS 465, Stereo Graphics Controller, 16" 120 Hz High Resolution Display and Liquid Crystal Shutter for IBM PC, 1989

Tektronix Inc, Beaverton, OR, $2,500.00, 90% School of Engineering and Science cost sharing for Model 4692, Color Ink-Jet Printer and Model 4510A, Color Ink-Jet Rasterizer with 2 Mbyte RAM expansion option, 1988

Tektronix Inc, Beaverton, OR, $5,995.00, 100% School of Engineering and Science cost sharing for Model 4315, Monochrome Workstation, 8 Mbyte RAM, 90 Mbyte HD, 1987 Memberships in Professional Societies

Phi Kappa Phi, 2004-present

IEEE Electron Devices Society Member, 2000-2016

IEEE Microwave Theory and Techniques Society Member, 2000-2016

Sigma Xi Society Member, 1994-present

IEEE Circuits and Systems Society Member, 1988-2016

IEEE Member, 1985-present