EE432/532 Microwave Circuit Design II: Lab 1
© B. Pejcinovic, P. Wong, O. Woywode

Introduction

This lab investigates the design of conditionally stable amplifiers using the technique of jointly matched terminations.

Design Specifications

Block diagram of FET amp

Figure 1: Block diagram of a FET amplifier

You are to design a single-stage amplifier using a transistor that is conditionally stable at the design frequency of f = 15 GHz. The process is outlined in the paper "A Deterministic Approach for Designing Conditionally Stable Amplifiers", authored by M. L. Edwards, S. Cheng, and J. H. Sinsky (IEEE Transactions on Microwave Theory and Techniques, VOL. 43, NO. 7, July 1995).

The core of the amplifier is a field effect transistor (FET) in common-source configuration. In MDS, there is a built-in model library for the Triquint GaAs (gallium arsenide) FET. This model has parameters that define the bias level for the FET, so you do not have to implement DC bias circuits. You may also omit the coupling capacitors.

There is a 50 ohm source impedance on the input side of the FET and a 50 ohm load on the output. To keep things simple, use ell circuits (i.e., capacitors and inductors) instead of microstrip to construct the input and output matching networks.

Jointly Matched Terminations Method

The basic task is to define a region inside the Gamma_s plane such that any Gamma_s within this region automatically results in a stable Gamma_L. The output stability circle is mapped into the Gamma_s plane. Depending on the device parameters, this translates into three different configurations (Figs. 4, 7, and 8 from the Edwards, Cheng, and Sinsky paper). The upper bound on gains resulting from jointly stable terminations is GMSM = 2*k*GMSG. For GA -> 0, the constant gain circle overlaps with the Smith chart unit circle. For GA -> infinity, the constant gain circle overlaps the input stability circle. Moreover, the centers of the input stability circle, unit circle, and all the constant gain circles are collinear.

Procedure:

  1. Compute k (preferred: 0.5 < k < 1)
  2. Compute D1 = |S11|2 - |delta|2 where delta = S11S22 - S12S21
  3. Compute K1 = |C1|2 - D12 where C1 = S11 - (delta)(S22*)
  4. Compare your results against Figs. 4, 7, and 8 from the Edwards, Cheng, and Sinsky paper. All conditions must be simultaneously met; otherwise, this method cannot be used.
  5. Compute GMSM = 2*k*(|S21|/|S12|)
  6. Choose GA <= GMSM - 2 dB for design robustness (allowing for parameter variations).
  7. Draw the GA = const. circle.
  8. Choose Gamma_s on the GA = const. circle.
  9. Design the input matching network (IMN).
  10. Attach the IMN to the transistor and simulate/measure Gamma_OUT.
  11. Design the output matching network for Gamma_L = conjugate(Gamma_OUT).

Questions

  1. Figure 3.3.9 on page 228 in the Gonzalez textbook (2nd edition) shows three different types of resistive loading configurations. Which one provides the best compromise? Think of noise and output power.
  2. For each of the following design methods, list some of their advantages and disadvantages:
    a) Resistive loading, b) Designing for GA, c) Jointly matched terminations.



FET Characteristics


Assignment

In this section, you will determine the operating characteristics of the Triquint FET.

Circuit construction

FET characterization test circuit

Figure 2: FET characterization test circuit

Simulation & Output

Items to turn in

Questions

  1. At the design frequency of 15 GHz, verify that the Triquint FET meets the requirements for using the jointly matched terminations method. Which configuration (Fig. 4, 7, or 8 from the Edwards, Cheng, and Sinsky paper) does the Triquint FET match?
  2. Comment on the magnitudes of S11 and S22. What are the important characteristics of a FET that would cause S11 and S22 to have such values?



Device Parameter Variation and Stability Boundaries


Assignment

You will examine how device parameter variation affects the input stability circle and gain circle, which then impacts the choice of Gamma_s and GA.

Parameter variations (sometimes as high as 20%) naturally occur in the manufacturing process. Thus, not all devices are identical. Accounting for this yields a more robust design. For this lab, assume that the gate width of the FET can vary by 10% about its nominal value of 50 um (micrometers).

Circuit construction

Device param variation test circuit

Figure 3: Device parameter variation test circuit

Simulation & Output

Items to turn in

Questions

  1. Briefly explain the behavior of the stability and gain circles as a function of the transistor's gate width.



Choosing Gamma_s


Assignment

Find the appropriate source reflection coefficient (Gamma_s) value for a design frequency of 15 GHz and an available gain of GA = GMSM - 2 dB (to allow for parameter variations).

Circuit construction

Gamma_s test circuit

Figure 4: Gamma_s test circuit

Simulation & Output

Smith chart with circles and line

Figure 5: Sample Smith chart with circles and added line

IMPORTANT: Repeat the simulation and output procedures at the extremes of the FET gate width, i.e. at W = 45 um and W = 55 um. Determine the corresponding Gamma_s value at each gate width.

Items to turn in

Questions

  1. What are the individual Gamma_s values (magnitude & phase) at W = 45 um, 50 um, and 55 um?
  2. Calculate the average Gamma_s and compare it to the value of Gamma_s at W = 50 um.



Designing the IMN


Assignment

You will design the input matching network (IMN) of the amplifier.

Circuit construction

IMN test circuit

Figure 6: IMN test circuit

Simulation & Output

IMPORTANT: Perform the simulation and output procedures at W = 45 um, 50 um, and 55 um. Determine the corresponding Gamma_OUT values at each gate width.

Items to turn in

Questions

  1. What are the individual Gamma_OUT values (magnitude & phase) at W = 45 um, 50 um, and 55 um?
  2. Compute the corresponding transducer gain GT for each value of Gamma_OUT.
  3. Calculate the average Gamma_OUT and compare it to the value of Gamma_OUT at W = 50 um.



Designing the OMN


Assignment

You will finish the amplifier circuit by designing the output matching network (OMN).

Circuit construction

Final amplifier circuit

Figure 7: Final amplifier circuit

Simulation & Output

Items to turn in

Questions

  1. What is the gain at the design frequency? Does it meet the design requirements (to within 2 or 3 percent)?
  2. Compare the magnitudes of S11 and S22 in the amplifier circuit with matching networks to their corresponding values with no matching networks.