I started my career at Intel in 1997 applying formal methods to the design and verification of leading edge microprocessors. In 2004, I left Intel to join Synplicity and worked on FPGA synthesis. In 2007, I joined Synopsys to work on emulation, prototyping, and constraint based verification. Since January 2019, I have been working at Cadence on leading edge EDA technologies. I am currently Vice President of R&D at Cadence.
William N. N. Hung,
"Effective and Scalable Verification: Bridging Research and Industry",
International Conference on Computer Aided Verification (CAV),
Invited Talk, San Francisco, California, July 2015.
Yongjian Li, William N. N. Hung,
and Xiaoyu Song,
"Automatically Exploring Structural Symmetry in Symbolic Trajectory Evaluation",
Hardware Verification Workshop (HWVW), Edinburgh, United Kingdom, July 2010.
Guowu Yang, Xiaoyu Song,
William N. N. Hung,
and Marek Perkowski,
"On Realization of 3-qubit Reversible Circuits with the minimum number of non-linear gates",
7th International Symposium on Representations and Methodology of Future Computing Technologies (RM2005),
Tokyo, Japan, September 2005.
Guowu Yang, Xiaoyu Song, Marek Perkowski, and
William N. N. Hung,
"Minimal Universal Library for nxn Reversible Circuits",
7th International Symposium on Representations and Methodology of Future Comp
uting Technologies (RM2005),
Tokyo, Japan, September 2005.
Guowu Yang,
William N. N. Hung,
Xiaoyu Song and Marek Perkowski,
"Majority-Based Reversible Logic Gate",
6th International Symposium on Representations and Methodology of Future
Computing Technologies (RM2003),
Trier, Germany, March 2003.
Xiaoyu Song, William N. N. Hung,
Alan Mishchenko, Malzorgata Chrzanowska-Jeske, Alan Coppola and Andrew Kennings,
"Board-Level
Multiterminal Net Assignment",
12th ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI),
New York, New York, April 2002.
N. N. William Hung, and Amiya Satapathy, "Systems and methods for distributed and parallelized emulation processor configuration", U.S. Patent No. 11868786, Issued January 9, 2024.
N. N. William Hung, and Dhiraj Goswami, "FPGA implementation interleaved with FPGA overlay architectures for emulation", U.S. Patent No. 11853668, Issued December 26, 2023.
N. N. William Hung, Yong Liu, and Michael Zimmer, "Method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth", U.S. Patent No. 11823018, Issued November 21, 2023.
N. N. William Hung, Dhiraj Goswami, Michael Zimmer, and Yong Liu, "Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference", U.S. Patent No. 11687831, Issued June 27, 2023.
Michael Zimmer, N. N. William Hung, Yong Liu, and Dhiraj Goswami, "Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis", U.S. Patent No. 11676068, Issued June 13, 2023.
Yong Liu, N. N. William Hung, and Michael Zimmer, "Method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights", U.S. Patent No. 11651283, Issued May 16, 2023.
N. N. William Hung, Dhiraj Goswami, Michael Patrick Zimmer, and Yong Liu, "Method, product, and apparatus for variable precision weight management for neural networks",
U.S. Patent No. 11615320, Issued March 28, 2023.
N. N. William Hung Qiang Qiang, Guillermo Maturana, Jasvinder Sing, and Dhiraj Goswami, "Optimizing constraint solving by rewriting at least one bit-slice constraint",
U.S. Patent No. 10372856, Issued August 6, 2019.
N. N. William Hung and Dhiraj Goswami,
"Generalized Resettable Memory",
U.S. Patent No. 9958917, Issued May 1, 2018.
Lingyi Liu, N. N. William Hung.
Sitanshu Seth, Leo Broukhis and Dhiraj Goswami,
"Formal method for clock tree analysis and optimization",
U.S. Patent No. 10325046, Issued June 18, 2019.
Dhiraj Goswami, N. N. William Hung,
"Information theoretic subgraph caching",
U.S. Patent No. 11468218, Issued September 21, 2022.
Dhiraj Goswami, N. N. William Hung,
"Information theoretic caching for dynamic problem generation in constraint solving",
U.S. Patent No. 9720792, Issued August 1, 2017.
Dhiraj Goswami, Soe Myint, N. N. William Hung, and Rajarshi Mukherjee,
"Identifying inconsistent constraints",
U.S. Patent No. 9069699, Issued June 30, 2015.