My research interests are in the general areas of
device physics, modeling and characterization and simulation.
Currently this research is focused in two areas:
·
The impact of models on the system level design and simulation
of convergence product mixed-signal ASICs, where GHz
analog functions are integrated with high-speed digital signal processing on
the same IC.
Personal Communications Systems are the focal point of these "Systems on a
Chip" which signal a convergence of technologies and disciplines:
communications, computing and audio/video signal processing.
In this area we’re currently working on functional simulation models of
nonlinear dynamic systems: phase-locked loops, Sigma-Delta converters and
digital modulation schemes. These functional models are characterized through
parameter extraction from transistor level simulation and data acquired from
measurements. When interfaced with traditional transistor models in critical
areas, these models allow for accurate and fast system simulation of large
mixed mode systems.
·
The development and integration of extraction
techniques, data management and simulation models for the
interconnect in very high frequency analog integrated circuits.
The quest for ever smaller feature size is driven by the demand for higher
performance: transistor speed and circuit complexity. Smaller feature sizes and
the accompanying feature proximity effects, combined with the higher operating
speeds, result in on-chip interconnect parasitics
playing an increasingly important role in determining signal integrity and
circuit performance.
In addition to resistive (ohmic drops, electromigration) and capacitive effects (cross-talk,
signal propagation delay, signal rise and fall time), in high-frequency systems
the self-inductance and mutual inductance in interconnect wires is a growing
concern. The impedance of a wire,
associated with self-inductance, (equal to wL), approaches or exceeds
the resistive impedance for frequencies above a few GHz. The mutual inductance
between adjacent conductors is a function of side wall area and wire pitch.
Moreover, as signal frequencies increase, the wavelength of those signals
approaches the physical dimensions on the chip. In this case the interconnect
starts to behave as a transmission line, which will need to be modeled as
coupled lossy transmission lines due to proximity
effects and non-ideal conductors and current return paths.
Thus trade-offs between wire size and pitch, hence density and cost, and signal
timing, signal integrity and noise need to be given serious consideration
during the IC design and analysis cycle. In the analog world, the current,
schematic-based, design flow isn’t well suited to include the cost/performance
trade-offs of interconnect parasitics.
Current and proposed thesis topics contain extra information about ongoing work.