"Methodology and Design of a Massively Parallel Memristive Stateful IMPLY Logic based Reconfigurable Architecture", Kamela C. Rahman, Dan Hammerstrom, Yiwei Li, Hongyan Castagnaro, and Marek A. Perkowski. Accepted for publication *IEEE Transactions on Nano-technology*.

"Coupled-Oscillator Associative Memory Array Operation for Pattern Recognition, " D. Nkonov, G. Csaba, W. Porod, T. Shibata, D. Voils, D., Hammerstrom, I. Young, and G. Bourianoff, *IEEE Journal on Exploratory Solid-State Computational Devices and Circuits*, Vol. 1, pp. 85-93, 2015.

"Performance/price estimates for cortex-scale hardware: A design space exploration," M.S. Zaveri, D. Hammerstrom, *Neural Networks*, (Archival Journal of the International Neural Network Society), Elsevier, 2010, DOI:10.1016/j.neunet.2010.12.003.

“Nano/CMOS implementations of Inference in Bayesian Memory – An Architecture Assessment Methodology,” Mazad S. Zaveri and Dan Hammerstrom, IEEE Transactions on Nanotechnology, Vol. 9, No. 2, March 2010, pp. 194-211. PDF

“CMOS/CMOL Architectures for Spiking Cortical Column,” C. Gao, M. S. Zaveri, D. Hammerstrom, Proceedings of IEEE World Congress on Computational Intelligence (WCCI) - Int. Joint Conf. on Neural Networks (IJCNN), June 1-6 2008, pp. 2442-2449. PDF

“Cortical Models onto CMOL and CMOS – Architectures and Performance/price,” Changjian Gao and Dan Hammerstrom, IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 54, No. 11, pp. 2502-2515, November 2007. PDF

“Architectures for Silicon Nanoelectronics and Beyond,” Iris Bahar, Justin Harlow, Dan Hammerstrom, William Joyner, Clifford Lau, Diana Marculescu, Alex Orailoglu, and Massoud Pedram, IEEE Computer, January 2007. PDF

“FPGA Implementation Of Very Large Associative Memories - Scaling Issues,” Changjian Gao, Dan Hammerstrom, Shaojuan Zhu, Mike Butts, Chapter submitted for book, FPGA Implementations of Neural Networks, Ed. Amos Omondi, Kluwer Academic Publishers, Boston, 2003. PDF

“Reinforcement Learning in Associative Memory,” Shaojuan Zhu and Dan Hammerstrom, IJCNN 03, July 2003. PDF

“Digital VLSI for Neural Networks,” Dan Hammerstrom, The Handbook of Brain Theory and Neural Networks, Second Edition, Ed. Michael Arbib, MIT Press, 2003.

“Comparing SFMD and SPMD Computation for On-Chip Multiprocessing of Intermediate Level Image Understanding Algorithms,” Steve Rehfuss and Dan Hammerstrom, Proceedings of the conference for Computer Architectures for Machine Perception 1997, Boston MA, October 1997. PDF

“Image Processing Using One-Dimensional Processor Arrays,” Dan Hammerstrom and Dan Lulich, The Proceedings of the IEEE, Vol. 84, No. 7, July 1996, pp. 1005-1018. PDF

“Model Matching and Single Function Multiple Data Computation (SFMD),” Steve Rehfuss and Dan Hammerstrom, NIPS Proceedings, November 1995. PDF

“A Digital VLSI Architecture for Real World Applications,” Dan Hammerstrom, An Introduction to Neural and Electronic Networks}, Electronic Networks, Edited by Steven F. Zornetzer, Joel L. Davis, Clifford Lau, and Tom McKenna, Academic Press, 1995. PDF

“Working with Neural Networks”, Dan Hammerstrom, IEEE Spectrum, July 1993, pp. 46-53.

“Neural Networks At Work”, Dan Hammerstrom, IEEE Spectrum, June 1993, pp. 26-32.

“The CNAPS Architecture for Neural Network Emulation”, Dan Hammerstrom, Wendell Henry, and Mike Kuhn, Parallel Digital Implementations of Neural Networks, Edited by K.W. Przytula and V.K. Prasanna Kumar, Prentice Hall, 1993, Engelwood Cliffs, NJ, pp 107-138.

“Why VLSI Implementations of Associative VLCNs Require Connection Multiplexing,” Jim Bailey and Dan Hammerstrom, Proceedings of the 1988 International Conference on Neural Networks, pp. 173-180, San Diego. PDF

“The Connectivity Requirements of Simple Association, or How Many Connections Do You Need?”, D. Hammerstrom, 1987 IEEE Conference on Neural Network Information Processing, pp. 338- 347. PDF