Architectures for Silicon Nanoelectronics and Beyond
A Workshop to Chart Research Directions
September 13-14, 2005
Portland State University
Presentations
Final Report Submitted to NSF
PDF
Opening Remarks, Bill Joyner, SRC
PDF
Abstracts for Presentations
PDF
Doing Real Computing With Nanoelectronics
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Neil Gershenfeld, Massachusetts Institute of
Technology, “Avogadro-Scale Engineering"
PDF
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John Carruthers, Portland State University,
,“Computing with Nanoelectronic Devices” PDF
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Konstantin Likharev, Stony Brook University,
“CMOL Circuits and their Possible Applications” PDF
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How Can We Make Reliable Systems from Unreliable
Nanodevices?
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Andre DeHon, California Institute of
Technology, “Strategies for Tolerating Highly Defective Fabrication and
Faulty Operation” PDF
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Valeriu Beiu, Washington State University,
“The Quest for Practical Redundant Computations” PDF
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Jose Fortes, University of Florida,
“Fundamental Models for Reliable Computation and Practical Implications”
PDF
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How Will We Use Nanoarchitectures?
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Kumar Wickramasinghe, IBM Almaden Research
Center, “Bridging the Gap from Micro to Nano – a New Multiplexing Device”
[No slides available yet, after IEDM?]
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Supriyo Bandyopadhyay, Virginia Commonwealth
University, “Self Assembled Cellular Neural Networks for Nanoelectronics"
PDF
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Lloyd Watts, Audience, Inc.,
“Biologically-Inspired Robust Sensory Systems” PDF
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Architectures for Human-Like Computing
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Dan Hammerstrom, Portland State University,
“Biologically Inspired Nanoscale Architecture”
PDF
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Sergey Lyshevski, Rochester Institute of
Technology, “Three Dimensional NanoBioArchitectronics: Towards
Super-High-Performance Computing Platforms” PDF
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Gary Bradski, Intel, "Substrate and
Superstructure for Computational Intelligence"
PDF
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Modeling and Simulation of Nanoscale Circuits and
Architectures
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Kaushik Roy, Purdue University, "Carbon
Nanotube Transistors: Modeling and Circuit Implications"
PDF
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Mircea Stan, University of Virginia,
“Circuit Design for Hybrid CMOS/Molecular Electronics”
PDF
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Alex Orailoglu, University of California San
Diego, “Order out of disorder: putting together functional nanoelectronics
systems” PDF
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Design Methodology and Design Tools for
Nanoarchitectures
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Seth Goldstein, Carnegie Mellon University,
“The Interaction of Tools, Circuits and Architectures at the Nanoscales”
PDF
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Mike Butts, Ambric, Inc., “How Can We Design
and Debug a Gigagate Chip?” PDF
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Charge to Groups, Bill Joyner, SRC
PDF
Group 1 Summary
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Group 2 Summary
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Group 3 Summary
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Comments PDF