Papers that refer to the research of our team. Papers that refer to the research of our team. FUNCTIONAL DECOMPOSITION A. Mishchenko, X. Wang, T. Kam. A New Enhanced Constructive Decomposition and Mapping Algorithm. J. Cortadella. Timing-Driven Logic Bi-Decomposition. IEEE Trans. on CAD. June 2003. A. Mishchenko, B. Steinbach, M. Perkowski. An Algorithm for Bi-Decomposition of Logic Functions. Bengtsson, Martinelli, Dubrova, A BDD-based fast heuristic algorithm for disjoint decomposition. In pdf format. J. Cortadella. Bi-Decomposition and tree-height reduction for timing optimization. IWLS'02. Bengtsson, Martinelli, Dubrova, A fast heuristic algorithm for disjoint decomposition of Boolean functions. In pdf format. V. Bertacco and M. Damiani, Boolean Function Representation Based on Disjoint-Support Decompositions. In pdf format. ICCD'96. Rawski, Luba, Jachna and Rzechowski, Functional Decomposition - The Value and Implication for Modern Digital Design. QUANTUM CIRCUITS A. Al-Rabadi and G. Lendaris, Artificial Neural Network Implementation Using Many-Valued Quantum Computing. IJCNN2003. In pdf format. EASILY TESTABLE CIRCUITS Nur A. Touba and Edward Mc Cluskey. RP-SYN: Synthesis of Random Pattern Testable Circuits with Test Point Insertion. IEEE Transactions on Computer Aided Design. T. Sasao. Easily Testable Realizations for Generalized Reed-Muller Expressions. IEEETC 1997. In pdf format. SYNTHESIS OF FINITE STATE MACHINES R. Puri, J. Gu. An Efficient Algorithm to Search for Minimal Closed Covers in Sequential Machines. N. Calazans. Pseudo-dichotomies and its use in simultaneous state minimization and state assignment. IFIP'92. In pdf format. M. Perkowski. Digital Design Automation: Finite State Machine Design. REVERSIBLE LOGIC SYNTHESIS. D. Maslov. Reversible Logic Synthesis. T. Sasao. Cascade Realizations of Two-valued Input Multiple-Valued Output Functions Using Decomposition of Group Functions. ISMVL 2003 EVOLVABLE AND LEARNING HARDWARE Miller. Review of First NASA/DOD Workshop on Evolvable Hardware 1999. Seok et al, Implementation of Genetic Programming on Evolvable Hardware for On-Line Adaptive Learning. DATA MINING AND MACHINE LEARNING. T. Windeatt, R. Tebbs. Spectral Technique for Hidden Layer Neural Network Training. K.B. Rangelov. Using the Multi-Valued Functional Decomposition to Evaluate Error in Machine Learning. K.B. Rangelov. Usefulness of the Multi-Valued Function in Machine Learning. Ch. Lang and B. Steinbach. Decomposition of Multi-Valued Functions into Min- and Max Gates. ISMVL'01. I. Guzman et al. Restricted Delta-Trees and Reduction Theorems in Multiple-Valued Logics. B. Zupan, M. Bohanec, J. Demsar, and I. Bratko. Learning by discovering concept hierarchies. AIJ'99. B. Zupan, M. Bohanec, J. Demsar, I. Bratko. Feature Transformation by Function Decomposition. IEEE Expert, 1998. RECONFIGURABLE COMPUTER ARCHITECTURES. L. Jozwiak, M. Perkowski and D. Foote. Massively Parallel Structures of Specialized Reconfigurable Cellular Processors for Fast Symbolic Computations. A. Carter. Using Dynamically Reconfigurable Hardware in Real-Time Communications Systems. Literature Survey. DECISION DIAGRAMS. D. Jankovic, R.S. Stankovic, and R. Drechsler. Decision Diagram Method for Calculation of Pruned Walsh Transform. IEEE Trans. on Comp. February 2001. D. Sieling. Lower Bounds for Linear Transformed OBDDs and FBDDs. B.Yang, Y.-A. Chen, R.E. Bryant and D.R. O'Hallaron. Space- and Time- Efficient BDD Construction via Working Set Control. ASP-DAC'98. C. Yang and M. Ciesielski. BDS: A BDD-Based Logic Optimization System. Trans. CAD. July 2002. R.E. Bryant. Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification. R.Drechsler, D. Sieling. Binary Decision Diagrams in Theory and Practice. W. Townsend, M. Thornton, R. Drechsler, D.M. Miller. Computing Walsh, Arithmetic, and Reed-Muller Spectral Decision Diagrams Using Graphs Transformations. Proc. GVLSI'2002. P. Lindgren, R. Drechsler, B. Becker, Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD'99. Main Date types. FUNCTIONAL REPRESENTATION. V. Bertacco and M. Damiani, Boolean Function Representation Using Parallel-Access Diagrams. In pdf format. G. Dueck et al. Development of Zakrevskij's Minimization Strategy towards Arithmetical Polynomial Domain. L. Shivakumaraiah and M.A. Thornton. Computation of Disjoint Cube Representations Using a Maximal Binate Variable Heuristic. TWO-LEVEL LOGIC SYNTHESIS. A. Mishchenko and T. Sasao. Large-Scale SOP Minimization Using Decomposition and Functional Properties. J. Hlavicka, P. Fiser. A Heuristic Method of Two-Level Logic Synthesis. P. Fiser, J. Hlavicka. Implicant Expansion Methods Used in the BOOM Minimizer. REGULAR FABRICS A. Sarabi, N. Song, M. Chrzanowska-Jeske, amd M. Perkowski. A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays. EXOR LOGIC SYNTHESIS. M. Helliwell, M. Perkowski. A Fast Algorithm to Minimize Multi-Output Mixed Polarity Generalized Reed-Muller Forms. Per Lindgren. Applications of Decision Diagrams in Digital Circuit Design. Yibin Ye and Kaushik Roy. Graph-Based Synthesis Algorithm for AND/XOR Networks. ROBOTICS. H.A. Yanco et al. Initial Report on Wheelesley: A Robotic Wheelchair System. IJCAI'95 INFORMATION MEASURES. L. Jozwiak. Information Relationships and Measures in Application to Logic Design. MULTIPLE-VALUED LOGIC. M. Gao, J-H Jiang, Y. Jiang, Y. Li, A. Mishchenko, S.Sinha, T. Villa, and R. Brayton. Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002. DESIGN AUTOMATION SYSTEMS. Jie-Hong Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa and R. Brayton. MVSIS V1.1. Manual. M. Perkowski, M. Driscoll, et al. Integration of Logic Synthesis and High-Level Synthesis into the Diades Design Automation System.