1. andrzej.pdf Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing
  2. cos.pdf Tomashev, Decomposition of Boolean Functions Targeted to Multiplexing.
  3. decomnp.pdf M. Venkatesan, "An Improved Input-Output Encoding Approach for Functional Decomposition".
  4. hanuliak.pdf I. Hanuliaj,J. Hanuliak, "To a Performance Evaluation of Parallel Algorithms".
  5. hlavicka.pdf Peter Fisher, Jan Hlavicka, "On the Use of Mutations in Boolean Minimization".
  6. jamro.pdf Ernest Jamro, Kazimierz Wiatr, "FPGA Implementation of Addition as a Part of the Convolution".
  7. kore.pdf M. Jung, Gueesang Lee, Sungju Park, "Minimization of PPKFDDs Using Genetic Algorithm".
  8. sanz.pdf "Pipelined Genetic Architecture with Fitness on the Fly".
  9. sequ.pdf E.San Millan, L. Entrena and J.A. Espejo, "On the Capabilities of Redundancy Addition and Removal for Sequential Logic Optimization".
  10. zaitseva.pdf E. Zaitseva, Dynamic Deterministic Reliability Indices".