This bibliography has not only positions in RL and QL but also other papers that are useful to understand them.


BIBLIOGRAPHY OF REVERSIBLE AND QUANTUM LOGIC AND COMPUTING



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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

ALPHABETICALLY

A
  1. W.C. Athas & L."J." Svensson, "Reversible Logic Issues in Adiabatic CMOS", Exploratory Design Group, University of Southern California - Information Sciences Institute, Marina del Rey, CA 90292-6695, {athas,svensson}@isi.edu
B


  1. H.G. Baker "(NREVERSAL) of Fortune - The Thermodynamics of Garbage Collection", Int'l Workshop on Memory Management, Y. Bekkers (ed.), Springer 1992, pp. 502-524.
  2. Ch.H. Bennett, "Notes on the History of Reversible Computation", IBM J. Res. Develop., Vol. 32, 1988, pp. 16-23.
  3. Ch. H. Bennett and R. Landauer, "The Fundamental Limits of Computation", Scientific American, July 1985, pp. 38-46.
  4. C. Bennett, "Logical reversibility of computation", I.B.M. Journal of Research and Development, 17 (1973), pp. 525-532.
  5. J. Birnbaum, "Computing Alternatives", Talk given on March 3, 1997 atACM97, March 3, 1997, San Jose, California, by Director of Hewlett- Packard Laboratories, Senior Vice-President of Research and Development.


C
  1. M. Chrzanowska-Jeske, Y. Xu, and M. Perkowski, ``Logic Synthesis for a Regular Layout,'' VLSI Design, Vol. 10, No. 1, pp. 35 - 55, 1999.
D
  1. B. Desoete, A. De Vos, M. Sibinski, T. Widerski, "Feynman's Reversible Logic Gates Implemented in Silicon", Proc. 6 th Intern. Conf. MIXDES, 1999, pp. 497-502.
E
F


  1. E. Fredkin, T. Toffoli, "Conservative Logic", Int. Journal of Theor. Phys., 21 (1982), pp. 219-253.
  2. R.Feynman, "Quantum Mechanical Computers", Optics News, 11 (1985), pp. 11-20.
  3. R. Feynman, "There's plenty of space at the bottom: an invitation To Enter a New Field of Physics," Nanotechnology, Ed BC Crandal and J.Lewis, the MIT Press 1992, pp. 347-363
  4. Feynman, R., "Feynman lectures on computation" (A. Hey and R. Allen, eds); Addison-Wesley, Reading (1996).
  5. M. Frank, "Physical Limits of Computing," CIS 4930.1194X / 6930.1078X, Spr. '00. WWW page
  6. Michael Frank, University of Florida.
  7. Nanotechnology from Frank.
  8. E.F. Fredkin, T. Toffoli, - Design Principles for Achieving High-Performance Submicron Digital Technologies, DARPA Proposal, Nov. 1978


G
H
I
J
K
  1. P. Kerntopf, "Logic Synthesis Using Reversible Gates," Proc. 3rd Symposium on Logic, Design and Learning, Portland, Oregon, May 31, 2000.
  2. P. Kerntopf, "A Comparison of Logical Efficiency of Reversible and Conventional Gates," 9th IEEE Workshop on Logic Synthesis,
  3. P. Kerntopf, "On Efficiency of Reversible Logic (3,3) Gates." Proc. 7th Intl. Conf. MIXDES, 2000, pp. 185-190.
  4. R. Keyes, and R. Landauer, "Minimal energy dissipation in logic"; I.B.M. Journal of Research and Development, 14 (1970), pp. 153-157.
  5. Z. Kohavi, "Switching Functions and Finite Automata Theory", Prentice Hall.
L
  1. R. Landauer, "Irreversibility and heat generation in the computational process"; I.B.M. Journal of Research and Development, 5 (1961), pp. 183-191.
  2. J. Lim, D. Kim, and S. Chae, "Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications," IEICE Trans. Electron, OL.E82 C, No. 4 April 1999.
M
  1. N. Margolus, "Physics and Computation", Ph. D. Thesis, Massachussets Institute of Technology, USA 1988.
  2. L.J. Micheel, A.H. Taddiken and A.C. Seabaugh, "Multiple-Valued Logic Computation Using Micro- and Nanoelectronic Devices," Proc. ISMVL, IEEE, 1993, pp. 164-169
  3. R C. Merkle and K. Eric Drexler, "Helical Logic", WWW.
  4. R C. Merkle, "Reversible electronic logic using switches," Nanotechnology, 4 (1993) pp. 21-40
  5. R. C. Merkle, "Two types of mechanical reversible logic," Nanotechnology, 4 (1993), pp. 114-131.
  6. O.N. Muzychenko, "Uniform and Regular Structures for Realization of Symmetric Functions of the Algebra of Logic", Automation and Remote Control, Vol. 59, No.4, 1998, pp. 581-592
N
  1. M.A. Nielsen and I.L. Chuang, "Quantum Computation and Quantum Information", Cambridge, 2001.
O
P
  1. Y.N. Patt, "A Complex Logic Module for the Synthesis of Combinational Switching Circuits", Proc. 30 th AFIPS Spring Joint Computer Conf., 1967, pp. 699-706.
  2. A. Peres, "Reversible Logic and Quantum Computers", Physical Review A, 32 (1985), pp. 3266-3276. [31]
  3. P. Picton, "Optoelectronic, Multivalued, Conservative Logic”, Int. Journal of Optical Computing, Vol. 2, 1991, pp. 19-29.
  4. P. Picton, "Multi-valued Sequential Logic Design Using Fredkin Gates", MVL Journal, vol.1, 1996, pp.241-251.
  5. P. D. Picton, "A Universal Architecture for Multiple-Valued Reversible Logic", WWW link
  6. P. Picton, "A Universal Architecture for Multiple-valued Reversible Logic," MVL Journal, 5 (2000), pp.27-37.
  7. P. Picton, "Modified Fredkin Gates in Logic Design," Microelectronics Journal, 25 (1994), pp. 437-441.
  8. M. A. Perkowski, "A Fundamental Theorem for EXOR Circuits," Proc. of IFIP W.G. 10.5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design," Hamburg, Germany, September 16-17, pp. 52 - 60, 1993.
  9. M. Perkowski, B. Falkowski, M. Chrzanowska-Jeske, and R. Drechlser, ``Efficient Algorithms for Creation of Linearly-Independent Decision Diagrams and their Mapping to Regular Layouts''. VLSI Design. In print
  10. Marek Perkowski, Pawel Kerntopf, Andrzej Buller, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Lech Jozwiak, Alan Coppola, "Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits," submitted.
  11. M.A. Perkowski, M. Chrzanowska-Jeske, and Y. Xu, ``Multi-Level Programmable Arrays for Sub-Micron Technology based on Symmetries,'' Proc. ICCIMA'98 Conference, pp. 707-720, February 1998, Australia, published by World Scientific.
  12. M.A. Perkowski. A. Al-Rabadi, P. Kerntopf, M. Chrzanowska-Jeske and A.Mishchenko, "Three Dimensional Realization of Multi-Valued Symmetric Functions using Reversible Logic". Submitted to ULSI 2001.
  13. M. Perkowski, P. Kerntopf, A. Buller, M. Chrzanowska-Jeske, A. Mishchenko, X. Song, A. Al-Rabadi, L. Jozwiak, A. Coppola, "Regular Realization of Symmetric Functions using Reversible Logic", submitted to Euro-Micro 2001.
  14. E. Pierzchala, M. A. Perkowski, S. Grygiel, "A Field Programmable Analog Arrray for Continuous, Fuzzy and Multi-Valued Logic Applications," Proc. ISMVL'94, pp. 148 - 155, Boston, MA, May 25-27, 1994.
Q
R


  1. Roska
  2. M.R. Rayner, D.J. Newton, "On the Symmetry of Logic", Journal of Physics A: Mathematical and General, 28 (1995), pp. 5623-5631.
  3. A.L. Ressler, - Practical Circuits Using Conservative Reversible Logic, Bachelor's Thesis, MIT 1979.


S


  1. Santa Fe.
  2. L. Storme, A. De Vos, G. Jacobs, "Group Theoretical Aspects of Reversible Logic Gates", Journal of Universal Computer Science, Vol. 5, 1999, pp. 307-321.
  3. G. Stix, "Riding the back of electrons"; Scientific American, 279 (September 1998), pp. 20-21.
  4. J. Shamir, H. J. Caulfield,
  5. W. Micelli, W., and R.I. Seymour, "Optical Computing and the Fredkin Gates", Applied Optics, 25, pp. 1604-1607, 1986.
  6. J.A. Smolin, and D.P. DiVincenzo, "Five Two-Bit Quantum Gates are sufficient to Implement the Quantum Fredkin Gate", Physical Review A, 53, pp. 2855-2856.
  7. A. Sarabi, N. Song, M. Chrzanowska-Jeske, M. A. Perkowski, "A Comprehensive Approach to Logic Synthesis and Physical Design for Two- Dimensional Logic Arrays," Proc. DAC'94, San Diego, June 1994, pp. 321 - 326.
  8. Stanford University.
  9. Sasao and Kinoshita consider the gates where the number of 1's in the inputs is equal to the number of 1's in the outputs. No fanout is permitted. Constant 1 is expensive. In the last paper, they consider the case where the number of 0's in the inputs is equal to the number of 0's in the outputs in addition to the restrictions above.
  10. TI = On magnetic bubble logic circuits

    AU = Kinoshita, K., Sasao, T., Matsuda, J. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)

    SO = IEEE Trans. Comput. (USA), vol.C-25, no.3, 247-53, MARCH 1976

    AB = This paper is concerned with the realisation of logic functions by using two-input magnetic bubble logic elements. A magnetic bubble logic element is the multiple-output logic element whose number of '1''s of the output is equal to that of corresponding input, and fanout of each output terminal of the element is restricted to one. In order to realize some functions, it is necessary to use the generators which correspond to constant-supplying elements. First, the number of generators which are necessary and sufficient to realize an arbitrary functions is obtained for a given set of elements. In particular, it is shown that an arbitrary function can be realized by using I/sub B/ elements and at most two generators. Since the I/sub B/ element is a universal element in the above sense and is considered to be rather easily realized by magnetic bubble interactions, the I/sub B/ logic circuits are mainly discussed. The I/sub B/ minimum circuit defined is a circuit which consists of minimum number of generators and minimum number of I/sub B/ elements. In the last half of this paper, it is shown that the minimum circuits of most functions have the characteristic circuit structure called '1-4 form.'.
  11. TI = Cascade realization of 3-input 3-output conservative logic circuits

    AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)

    SO = IEEE Trans. Comput. (USA), vol.C-27, no.3, 214-21, MARCH 1978

    AB = A conservative logic element (CLE) is a multiple-output logic element whose weight of an input vector is equal to that of the corresponding output vector, and is a generalized model of magnetic bubble logic elements, fluid logic elements, and so on. This paper considers the problem of realizing arbitrary 3-input 3-output conservative logic elements (3-3 CLCs) by cascade connections of 3-input 3-output CLEs called 'primitives'. It is shown that the necessary and sufficient number of different primitives to realize an arbitrary 3-3 CLC is three in the case when the crossovers of lines are permitted, and four in the case when the crossovers of lines are not permitted.
  12. TI = Realization of minimum circuits with two-input conservative logic elements

    AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)

    SO = IEEE Trans. Comput. (USA), vol.C-27, no.8, 749-52, Aug. 1978

    AB = This correspondence is concerned with the realization of logical functions by using two input three output conservative logic elements called I/sub B/. A conservative logic element is a multiple-output logic element whose number of '1s' of the input is equal to that of the corresponding output, and whose fan out of each output terminal is restricted to one. In order to realize arbitrary functions, it is necessary to use constant-supplying elements C/sub 1/s. The minimum circuit is a circuit which consists of minimum number of C/sub 1/s and minimum number of I/sub B/ elements. This correspondence gives lower bounds on the number of I/sub B/ elements in the circuit and two minimum decomposition theorems. These results are useful for the verification of the minimality of a given circuit and for the realization of minimum circuits. Several examples illustrate this.
  13. TI = Conservative logic elements and their universality

    AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)

    SO = IEEE Trans. Comput. (USA), vol.C-28, no.9, 682-5, Sept. 1979

    AB = A conservative logic element (CLE) is a multiple-output logic element whose weight of an input vector is equal to that of the corresponding output vector, and fan-out of each output terminal is restricted to one.

    A CLE is a generalized model of magnetic bubble logic elements, etc. In order to realize an arbitrary function, it is necessary to use constant-supplying elements (CSEs).


T


  1. T. Toffoli, "Reversible Computing", in Automata, Languages and Programming, Springer Verlag, 1980, pp. 632- 644.
  2. T. Toffoli, - Reversible Computing, MIT Lab for Computer Science, Technical memo MIT/LCS/TM-151, Feb 1980 (out of print, available from NTIS)


U
W
  1. P. Wayner, "Silicon in Reverse", Byte Magazine, August 1994, page 67.
  2. A workshop on the Physics of Computation was held at MIT in 1981; the papers were printed in the April, June and December issues of the 1982 International Journal for Theoretical Physics, Volume 21.
V
  1. V. I. Varshavsky, "Logic Design and Quantum Challenge". Preprint from the author.
  2. A. De Vos, B. Desoete, A. Adamski, P. Pietrzak, M. Sibinski, T. Widerski "Design of reversible circuits by means of control gates", Integrated Circuit Design, Proc. PATMOS'2000 (10th Workshop Power and Timing Modeling, Optimization and Simulation), Goettingen, Germany, Sept. 13-15, 2000, P. Pirsch and E. Barke (eds.), Springer Verlag, Lecture Notes in Computer Science, vol. 1918, pp.255-264. See Kerntopf.
  3. A. De Vos, "Proposal for an Implementation of Reversible Gates in c-MOS," Int. Journal of Electronics, Vol. 76, 1994, pp. 293-302.
  4. A. De Vos, "Reversible Computing in c-MOS”, Proc. Advanced Training Course on Mixed Design of VLSI Circuits, 1994, pp. 36-41.
  5. A. De Vos, "A 12-Transistor c-MOS Building-Block for Reversible Computers", Int. Journal of Electronics, Vol. 79, 1995, pp. 171-182.
  6. A. De Vos, "Reversible and Endoreversible Computing", Int. Journal of Theor. Phys., Vol. 34, 1995, pp. 2251-2266.
  7. De Vos, A., "Introduction to r-MOS systems"; Proc. 4 th Workshop on Physics and Computation, Boston, 1996, pp. 92-96.
  8. De Vos, A., "Towards reversible digital computers"; Proc. European Conference on Circuit Theory and Design, Budapest, 1997, pp. 923-931.
  9. De Vos, A., "Reversible computing"; Progress in Quantum Electronics, 23 (1999), pp. 1-49.
X
Y
  1. T. Yang, K.R. Crounse, L.O. Chua, "Application of Reversible Discrete-Time Cellular Neural Networks to Image Copyright Labeling", Proceedings of IEEE Int. Workshop on Cellular Neural Networks and Their Applications, (CNNA'96), pp.19-24, Sevilla, 1996,
Z