This bibliography has not only positions in RL and QL but also other papers that are
useful to understand them.
BIBLIOGRAPHY OF REVERSIBLE AND QUANTUM LOGIC AND COMPUTING
BACK TO MAIN PAGE OF Professor Marek Perkowski
ALPHABETICALLY
A

W.C. Athas & L."J." Svensson,
"Reversible Logic Issues in Adiabatic CMOS", Exploratory
Design Group, University of Southern California  Information Sciences
Institute, Marina del Rey, CA 902926695, {athas,svensson}@isi.edu
B

H.G. Baker
"(NREVERSAL) of Fortune  The Thermodynamics of Garbage Collection", Int'l Workshop
on Memory Management, Y. Bekkers (ed.), Springer 1992, pp. 502524.

Ch.H. Bennett,
"Notes on the History of Reversible Computation", IBM J. Res. Develop., Vol. 32, 1988, pp. 1623.

Ch. H. Bennett and R. Landauer,
"The Fundamental Limits of Computation",
Scientific American, July 1985, pp. 3846.

C. Bennett,
"Logical reversibility of computation", I.B.M. Journal of Research and Development, 17 (1973), pp. 525532.

J. Birnbaum,
"Computing Alternatives",
Talk given on March 3, 1997 atACM97, March 3, 1997, San Jose, California, by Director of Hewlett
Packard Laboratories, Senior VicePresident of Research and Development.
C

M. ChrzanowskaJeske, Y. Xu, and M. Perkowski,
``Logic Synthesis for a Regular
Layout,'' VLSI Design, Vol. 10, No. 1, pp. 35  55, 1999.
D

B. Desoete, A. De Vos, M. Sibinski, T. Widerski,
"Feynman's Reversible Logic Gates Implemented in Silicon", Proc. 6 th Intern. Conf.
MIXDES, 1999, pp. 497502.
E

F

E. Fredkin, T. Toffoli,
"Conservative Logic", Int. Journal of Theor. Phys., 21 (1982), pp. 219253.

R.Feynman,
"Quantum Mechanical Computers", Optics News, 11 (1985), pp. 1120.

R. Feynman,
"There's plenty of space at the bottom: an invitation To Enter a New Field of Physics,"
Nanotechnology, Ed BC Crandal and J.Lewis, the MIT Press 1992, pp.
347363

Feynman, R.,
"Feynman lectures on computation"
(A. Hey and R. Allen, eds); AddisonWesley, Reading (1996).

M. Frank,
"Physical Limits of Computing,"
CIS 4930.1194X / 6930.1078X, Spr. '00. WWW page
 Michael Frank, University of Florida.
 Nanotechnology from Frank.

E.F. Fredkin, T. Toffoli,
 Design Principles for Achieving HighPerformance Submicron Digital
Technologies, DARPA Proposal, Nov. 1978
G

H

I

J

K

P. Kerntopf,
"Logic Synthesis Using Reversible Gates,"
Proc. 3rd Symposium on Logic, Design and Learning,
Portland, Oregon, May 31, 2000.

P. Kerntopf,
"A Comparison of Logical Efficiency of
Reversible and Conventional Gates,"
9th IEEE Workshop on Logic Synthesis,

P. Kerntopf,
"On Efficiency of Reversible Logic (3,3) Gates."
Proc. 7th Intl. Conf. MIXDES, 2000, pp. 185190.

R. Keyes, and R. Landauer,
"Minimal energy dissipation in logic"; I.B.M. Journal of Research and
Development, 14 (1970), pp. 153157.

Z. Kohavi,
"Switching Functions and Finite Automata Theory", Prentice Hall.
L

R. Landauer,
"Irreversibility and heat generation in the computational process"; I.B.M. Journal of
Research and Development, 5 (1961), pp. 183191.

J. Lim, D. Kim, and S. Chae,
"Reversible Energy Recovery Logic Circuits and Its
8Phase Clocked Power Generator for UltraLowPower Applications,"
IEICE Trans. Electron, OL.E82 C, No. 4 April 1999.
M

N. Margolus,
"Physics and Computation", Ph. D. Thesis, Massachussets Institute of Technology, USA 1988.

L.J. Micheel, A.H. Taddiken and A.C.
Seabaugh, "MultipleValued Logic Computation Using Micro and Nanoelectronic Devices,"
Proc. ISMVL, IEEE, 1993, pp. 164169

R C. Merkle and K. Eric Drexler,
"Helical Logic", WWW.

R C. Merkle,
"Reversible electronic logic using switches," Nanotechnology, 4 (1993)
pp. 2140

R. C. Merkle,
"Two types of mechanical reversible logic,"
Nanotechnology, 4 (1993), pp. 114131.

O.N. Muzychenko,
"Uniform and Regular Structures for
Realization of Symmetric Functions of the Algebra of Logic",
Automation and Remote Control, Vol. 59, No.4, 1998, pp. 581592
N

M.A. Nielsen and I.L. Chuang,
"Quantum Computation and Quantum Information", Cambridge, 2001.
O

P

Y.N. Patt,
"A Complex Logic Module for the Synthesis of Combinational Switching Circuits",
Proc. 30 th AFIPS Spring Joint Computer Conf., 1967, pp. 699706.

A. Peres,
"Reversible Logic and Quantum Computers", Physical Review A, 32 (1985), pp. 32663276. [31]

P. Picton,
"Optoelectronic, Multivalued, Conservative Logic”, Int. Journal of Optical Computing, Vol. 2,
1991, pp. 1929.

P. Picton,
"Multivalued Sequential Logic Design Using Fredkin Gates", MVL Journal,
vol.1, 1996, pp.241251.

P. D. Picton,
"A Universal Architecture for MultipleValued Reversible Logic",
WWW link

P. Picton,
"A Universal Architecture for Multiplevalued Reversible Logic," MVL
Journal, 5 (2000), pp.2737.

P. Picton,
"Modified Fredkin Gates in Logic Design," Microelectronics Journal,
25 (1994), pp. 437441.

M. A. Perkowski,
"A Fundamental Theorem for EXOR Circuits," Proc. of IFIP W.G.
10.5 Workshop on Applications of the ReedMuller
Expansion in Circuit Design," Hamburg, Germany, September 1617, pp. 52  60, 1993.

M. Perkowski, B. Falkowski, M. ChrzanowskaJeske, and R. Drechlser,
``Efficient
Algorithms for Creation of LinearlyIndependent Decision
Diagrams and their Mapping to Regular Layouts''. VLSI Design. In print

Marek Perkowski, Pawel Kerntopf, Andrzej Buller, Malgorzata ChrzanowskaJeske,
Alan Mishchenko, Xiaoyu Song, Anas AlRabadi, Lech Jozwiak, Alan Coppola,
"Regularity and Symmetry as a Base for Efficient Realization of Reversible Logic Circuits,"
submitted.

M.A. Perkowski, M. ChrzanowskaJeske, and Y. Xu,
``MultiLevel Programmable Arrays for SubMicron Technology based on Symmetries,''
Proc. ICCIMA'98 Conference, pp. 707720, February 1998, Australia, published by World Scientific.

M.A. Perkowski. A. AlRabadi, P. Kerntopf, M. ChrzanowskaJeske and A.Mishchenko,
"Three Dimensional Realization of MultiValued
Symmetric Functions using Reversible Logic". Submitted to ULSI 2001.

M. Perkowski, P. Kerntopf, A. Buller, M. ChrzanowskaJeske, A. Mishchenko, X. Song, A. AlRabadi, L. Jozwiak, A. Coppola,
"Regular Realization of Symmetric Functions using Reversible Logic", submitted to EuroMicro 2001.

E. Pierzchala, M. A. Perkowski, S. Grygiel,
"A Field Programmable Analog Arrray
for Continuous, Fuzzy and MultiValued Logic
Applications," Proc. ISMVL'94, pp. 148  155, Boston, MA, May 2527, 1994.
Q

R

Roska

M.R. Rayner, D.J. Newton, "On the Symmetry of Logic",
Journal of Physics A: Mathematical and General, 28 (1995),
pp. 56235631.

A.L. Ressler,
 Practical Circuits Using Conservative Reversible Logic, Bachelor's Thesis, MIT 1979.
S

Santa Fe.

L. Storme, A. De Vos, G. Jacobs,
"Group Theoretical Aspects of Reversible Logic Gates",
Journal of Universal Computer Science, Vol. 5, 1999, pp. 307321.

G. Stix,
"Riding the back of electrons"; Scientific American,
279 (September 1998), pp. 2021.

J. Shamir, H. J. Caulfield,

W. Micelli, W., and R.I. Seymour,
"Optical Computing and the Fredkin Gates",
Applied Optics, 25, pp. 16041607, 1986.

J.A. Smolin, and D.P. DiVincenzo,
"Five TwoBit Quantum Gates are sufficient to Implement the Quantum Fredkin Gate",
Physical Review A, 53, pp. 28552856.

A. Sarabi, N. Song, M. ChrzanowskaJeske, M. A. Perkowski,
"A Comprehensive Approach to Logic Synthesis and Physical Design for Two
Dimensional Logic Arrays," Proc. DAC'94, San Diego, June 1994, pp. 321  326.
 Stanford University.

Sasao and Kinoshita consider the gates where the number of 1's in the inputs
is equal to the number of 1's in the outputs. No fanout is permitted. Constant 1 is expensive.
In the last paper, they consider the case where
the number of 0's in the inputs is equal to the number of 0's
in the outputs in addition to the restrictions above.

TI = On magnetic bubble logic circuits
AU = Kinoshita, K., Sasao, T., Matsuda, J. (Dept. of Electronic Engng.,
Osaka Univ., Osaka, Japan)
SO = IEEE Trans. Comput. (USA), vol.C25, no.3, 24753, MARCH 1976
AB = This paper is concerned with the realisation of logic functions by
using twoinput magnetic bubble logic elements. A magnetic bubble logic
element is the multipleoutput logic element whose number of '1''s of
the output is equal to that of corresponding input, and fanout of each
output terminal of the element is restricted to one. In order to
realize some functions, it is necessary to use the generators which
correspond to constantsupplying elements. First, the number of
generators which are necessary and sufficient to realize an arbitrary
functions is obtained for a given set of elements. In particular, it is
shown that an arbitrary function can be realized by using I/sub B/
elements and at most two generators. Since the I/sub B/ element is a
universal element in the above sense and is considered to be rather
easily realized by magnetic bubble interactions, the I/sub B/ logic
circuits are mainly discussed. The I/sub B/ minimum circuit defined is
a circuit which consists of minimum number of generators and minimum
number of I/sub B/ elements. In the last half of this paper, it is
shown that the minimum circuits of most functions have the
characteristic circuit structure called '14 form.'.

TI = Cascade realization of 3input 3output conservative logic circuits
AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ.,
Osaka, Japan)
SO = IEEE Trans. Comput. (USA), vol.C27, no.3, 21421, MARCH 1978
AB = A conservative logic element (CLE) is a multipleoutput logic element
whose weight of an input vector is equal to that of the corresponding
output vector, and is a generalized model of magnetic bubble logic
elements, fluid logic elements, and so on. This paper considers the
problem of realizing arbitrary 3input 3output conservative logic
elements (33 CLCs) by cascade connections of 3input 3output CLEs
called 'primitives'. It is shown that the necessary and sufficient
number of different primitives to realize an arbitrary 33 CLC is three
in the case when the crossovers of lines are permitted, and four in the
case when the crossovers of lines are not permitted.

TI = Realization of minimum circuits with twoinput conservative logic elements
AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)
SO = IEEE Trans. Comput. (USA), vol.C27, no.8, 74952, Aug. 1978
AB = This correspondence is concerned with the realization of logical
functions by using two input three output conservative logic elements
called I/sub B/. A conservative logic element is a multipleoutput
logic element whose number of '1s' of the input is equal to that of the
corresponding output, and whose fan out of each output terminal is
restricted to one. In order to realize arbitrary functions, it is
necessary to use constantsupplying elements C/sub 1/s. The minimum
circuit is a circuit which consists of minimum number of C/sub 1/s and
minimum number of I/sub B/ elements. This correspondence gives lower
bounds on the number of I/sub B/ elements in the circuit and two
minimum decomposition theorems. These results are useful for the
verification of the minimality of a given circuit and for the
realization of minimum circuits. Several examples illustrate this.

TI = Conservative logic elements and their universality
AU = Sasao, T., Kinoshita, K. (Dept. of Electronic Engng., Osaka Univ., Osaka, Japan)
SO = IEEE Trans. Comput. (USA), vol.C28, no.9, 6825, Sept. 1979
AB = A conservative logic element (CLE) is a multipleoutput logic element
whose weight of an input vector is equal to that of the corresponding
output vector, and fanout of each output terminal is restricted to one.
A CLE is a generalized model of magnetic bubble logic elements,
etc. In order to realize an arbitrary function, it is necessary to use
constantsupplying elements (CSEs).
T

T. Toffoli,
"Reversible Computing", in Automata, Languages and Programming, Springer Verlag, 1980, pp. 632 644.

T. Toffoli,
 Reversible Computing, MIT Lab for Computer Science, Technical memo MIT/LCS/TM151,
Feb 1980 (out of print, available from NTIS)
U

W

P. Wayner,
"Silicon in Reverse", Byte Magazine, August 1994, page 67.

A workshop on the Physics of Computation was held
at MIT in 1981; the papers were printed in the April, June and December issues of the
1982 International Journal for Theoretical Physics, Volume 21.
V

V. I. Varshavsky,
"Logic Design and Quantum Challenge". Preprint from the author.

A. De Vos, B. Desoete, A. Adamski, P. Pietrzak, M. Sibinski, T. Widerski
"Design of reversible
circuits by means of control gates", Integrated Circuit Design, Proc. PATMOS'2000 (10th Workshop
Power and Timing Modeling, Optimization and Simulation), Goettingen, Germany, Sept. 1315, 2000,
P. Pirsch and E. Barke (eds.), Springer Verlag, Lecture Notes in Computer Science, vol. 1918,
pp.255264.
See Kerntopf.

A. De Vos,
"Proposal for an Implementation of Reversible Gates in cMOS,"
Int. Journal of Electronics, Vol. 76, 1994, pp. 293302.

A. De Vos,
"Reversible Computing in cMOS”, Proc. Advanced Training Course on Mixed Design of VLSI Circuits, 1994, pp. 3641.

A. De Vos,
"A 12Transistor cMOS BuildingBlock for Reversible Computers",
Int. Journal of Electronics, Vol. 79, 1995, pp. 171182.

A. De Vos,
"Reversible and Endoreversible Computing", Int. Journal of Theor. Phys., Vol. 34, 1995, pp. 22512266.

De Vos, A.,
"Introduction to rMOS systems";
Proc. 4 th Workshop on Physics and Computation, Boston, 1996, pp. 9296.

De Vos, A.,
"Towards reversible digital computers";
Proc. European Conference on Circuit Theory and Design, Budapest, 1997, pp. 923931.

De Vos, A.,
"Reversible computing"; Progress in
Quantum Electronics, 23 (1999), pp. 149.
X

Y

T. Yang, K.R. Crounse, L.O. Chua,
"Application of Reversible DiscreteTime Cellular Neural Networks to Image Copyright Labeling",
Proceedings of IEEE Int. Workshop on Cellular Neural Networks and Their Applications,
(CNNA'96), pp.1924, Sevilla, 1996,
Z