Table of contents Thirty IEEE International Symposium on Multi-Valued Logic (ISMVL'00) Message from the Symposium Chair Message from the Program Co-Chairs Symposium Committee Referees Session 1: Invited address Computational Neurobiology Meets Semiconductor Engineering Dan Hammerstrom Session 2a: Neural and Threshold Nets Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors J. Shen, M. Inaba, K. Tanno, O. Ishizuka The Synthesis of the Multiple-Valued Logic Circuits by Using the Local-Excitation-Type Neuron Models M. Matumoto, Y. Ueda, I. Nomoto Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions M. Syuto, J. Shen, K. Tanno, O. Ishizuka The Computing Capacity of Three-Input Multiple-Valued One-Threshold Perceptrons, A. Ngom, I. Stojmenovic, R. Tosic Session 2b: Spectral Methods MDD-based Synthesis of Multi-Valued Logic Networks M. Thornton Fast Transforms for Multiple-Valued Input Binary Output PLI Logic B. J. Falkowski and S. Rahardja Computation of Spectral Information from Boolean Netlist R. Drechsler, M. A. Thornton Fault Analysis of the Multiple-Valued Logic using Spectral Method J. O. Kim, Y. G. Kim, P. Lala, H. S. Kim Session 3: Invited Address Neural and Fuzzy Computing J. Zurada Session 4a: Decomposition and Data Mining Data Mining of Weak Functional Decomposition S. Jaroszewicz, and D. Simovici Multi-Valued Sub-functions Encoding in Functional Decomposition Based on Information Relationship Measure A. Chojnacki, and L. Jozwiak On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions T. Sasao Session 4b: Algebra I Rigidity problems of autodual clones M. Miyakawa, I. G. Rosenberg Some Properties of Discrete Interval Truth Values Logic N. Takagi and K. Nakashima On Urguhart's C Logic A. Ciabattoni Session 5a: Fuzzy Logic A New Class of Fuzzy Modifiers M. DeCock, E. Kerre Fuzzy Decision Diagrams for the Presentation of Rule Bases K. Strehl, C. Moraga, K.-H.Temme, R. S. Stankovic On Algebraic Formulation of Information Granulation III Investigation the Hata-Mukaidono Approach H. Thiele Session 5b: Reed-Muller Logic and Its Extensions Experiments on FPRM Expressions for Partially Symmetric Logic Functions, S.N. Yanushkevich, J.T. Butler, G. Dueck, V. Shmerko Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams H. M. H. Babu, T. Sasao A New Algorithm to Compute Quaternary Reed-Muller Expansions S. Rahardja, B.J. Falkowski Session 6: Invited Address Evolvable Hardware: from on-chip circuit synthesis to Evolvable Space Systems A. Stoica Session 7a: Logic and Algebra De Morgan Bisemilattices J.A. Brzozowski Finite-Valued Approximation of Product Logic S. Aguzzoli, B. Gerla Integration of Information in Four-Valued Logics under Non-Uniform Assumption Y. Loyer, N. Spyratos, D. Stamate Session 7b: Decision Diagrams Lower Bound Sifting for MDDs D. Jankovic, W. Guenter, R. Drechsler, Implementation of Multiple-Output Functions using PQMDDs Y. Iguchi, T. Sasao, M. Matsuura Fibonacci Decision Diagrams and Fibonacci Spectral Decision Diagrams S. Stankovic, M. Stankovic, J.T. Astola, K. Egiazairan, Session 8a: Circuits I Cost-Analysis of 4-Valued Unary Functions Implemented using Current-Mode CMOS Circuits M. Abd-El-Barr, A. Al-Mutawa Implementation of Multiple-Valued Multiplier on GF(3^m) using Current Mode CMOS H.K. Seong, J.S. Choi, B.S. Shin, H.S. Kim Novel Pi-Type Resistor Network in D/A Converter based on multiple-valued logic X. Wu, X. Zhou Session 8b: Decision Diagrams and Test Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions H. Sack, E. Dubrova, Ch. Meinel Dynamic Re-Encoding During MDD Minimization F.Schmiedle, W.Guenter, R.Drechsler Controllability-Observability Measures for Multiple-Valued Test Generation Based on D-algorithm M. Kamiura and Y. Hata Session 9a: Evolutionary and Information Theory Approaches Evolutionary Multi-Level Circuit Synthesis in Given Design Style T. Luba, S.N. Yanushkevich, M. Opoka, C. Moraga, V.Shmerko An Evolutionary Computing Approach to Multiple-Valued Logic Synthesis Using Various Logic Operations T. Hozumi, O. Kakusho and K.Yamato Information Theory Approach for Mimimization of Polynomial Expressions over GF(4) S.N. Yanushkevich, D.V. Popel, V.A. Cheushev, V.P. Shmerko, R.S. Stankovic Session 9b: Image and Language Processing On the Architecture of Medical Image Registration System Based on Multiple-Valued Logic Y. Hata, S. Kobashi, N. Kamiura, Y. Kitamura, T. Yanagida Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra B.J. Falkowski, L. S. Lim 
15:15 - 15:45   A Four-Valued Logic B(4) of E(9) for Modelling Human 
                Spoken and Written Dialog

                D. Rine, and R. Alnakari,
                George Mason University, USA
                
Session 10:  Invited Address

Structures with many-valued information 
and their relational proof theory
Ewa Orlowska 

Session 11a: Circuits II 

A Novel Multiple-Valued T-Gate using
Multiple-Junction Surface Tunnel Transisters 
and Its Application to Three-valued Data Flip-Flop
T. Uemura, T. Baba

A Study on the Ternary Parallel Circuit
Design with DCG properties based on the Matrix Equation
G. N. Byun, C. U. Lee, S. Y. Park, H. S. Kim,
                 
Novel Resonant-Tunneling Multiple-Threshold
Logic Circuit Based on Switching Sequence Detection
T. Waho, K. Hattori, K. Honda

Standard CMOS Implementation of a Multiple-Valued Logic
Signed-Digit Adder Based on Negative
Differential-Resistance Devices
A.G. Gonzalez, M. Bhattacharya, S. Kulkarni, P. Mazumder 

Session 11b:  Theorem-Proving and Applications          

The 2-SAT Problem of Regular Signed CNF Formulas
B. Beckert, R. Haenhle, Felip Manya 

Chaining Techniques for Automated Theorem Proving
in Many-Valued Logics,
H. Ganzinger, V. Sofronie-Stokkermans 

High-Radix Parallel VLSI Dividers
 without Using Quotient Digit Selection Tables
T. Aoki, K. Nakazawa, T. Higuchi 

Session 12: Invited Address

???
Marvan Jabri

Session 13: Panel Discussion 

Multiple-Valued Logic: Provocative questions.

Session 14: Invited Address                            

Intel Flash-Strata. Multi-valued Memory.
Greg Atwood

Session 15: Circuits III

Hardware Implementation of "Supplementary Symmetrical Logic
Circuit Structure" Concepts
Dan Olson, K.W. Current

Design of Quaternary Latch Circuit
Using a Binary CMOS RS Latch, 
K.W. Current 

Low-Power Dual-Rail Multiple-Valued Current-Mode
Logic Circuit Using Multiple Input-Signal Levels
T. Hanyu, T. Ike, M. Kameyama 

Session 14b: Algebra II                               

Clarifying the Axioms of Boolean Algebra
based on the Method of Indeterminate Coefficients
T. Ninomiya, M.Mukaidono 

Maximal and Minimal Partial Clones
L. Haddad, H. Machida, I.G. Rosenberg 

Logic Synthesis of Controllers 
for B-ternary Asynchronous Systems
Y. Nagata, D.M. Miller, M. Mukaidono 

Session 15: Invited Address                           

Silicon Single-Electron Devices and their Applications
Yasuo Takahashi

Session 16a: Arithmetics and Systems 

Dram-Cell-Based Multiple-Valued
Logic-in-Memory VLSI with Charge Addition and Charge Storage
T. Hanyu, H. Kimura, M. Kameyama 
                
An Efficient Data Transmission Technique 
for VLSI Systems based on Multiple-Valued
Code-Division Multiple Access
Y. Yuminaka, O, Katoh, Y. Sasaki, T. Aoki, T. Higuchi
                
Arithmetic-Oriented Multiple-Valued Logic-in-Memory
VLSI Based on Current-Mode Logic
S. Kaeriyama, T. Hanyu, M. Kameyama

Session 16b: Verification and Power Estimation              

A Method for Approximate Equivalence Checking
M. Thornton, R. Drechsler, W. Guenter 

Propagation algorithm of behavior probability in
power estimation based on multiple-valued logic
X. Wu, M. Pedram 

Probabilistic verification of Multiple-Valued Functions
E. Dubrova, H. Sack

18:45 - 19:00   Closing remarks