10:00 - 10:20 Registration 10:20 - 10:30 Opening remarks Room PCAT 138
Alan Mishchenko, Workshop Organizer
Session 1: Tutorial Talks Room PCAT 138 Chair: T. Sasao
10:30 - 11:15 What is Multiple-Valued Logic: A Point of View
M. Perkowski, Portland State University, USA
11:15 - 12:00 Implicit Methods for Logic Synthesis, Test and Verification
A. Mishchenko, Portland State University, USA
12:00 - 13:00 Lunch
Session 2: Learning Room PCAT 138 Chair: M. Kameyama
13:00 - 13:45 Invited speaker in learning theory
13:20 - 13:40 A New Evolutionary Approach to Design and Learning
K. Dill, Portland State University, USA
13:40 - 14:00 Machine Learning Using New Decomposition Approach
C. Files, Portland State University, USA
14:00 - 14:20 Robots that Learn
M. Perkowski, Portland State University, USA
14:20 - 14:40 Refreshment break
Session 3: Representation Room PCAT 138 Chair: D. Simovici
14:40 - 15:20 Universal Wavelet Decision Diagrams
A. Al-Rabadi, Portland State University, USA15:20 - 16:00 Multi-Way Decision DiagramsX. Song, Portland State University, USA
16:00 - 16:20 Refreshment break
Session 4: Software and Robotics Chair: S. Yanushkevich
16:20 - 16:40 Software and robot learning demonstrations,
A. Mishchenko, Portland State University, USA. 16:40 - 17:00 M. Jeske ??? 17:00 - 17:20 L. Jozwiak??? 17:20 - 17:40 T. Luba ??? Zwick? Garrison Greenwood?? Allen Taylor???
18:00 ISMVL 2000 Welcome Reception, wine and cheese.
Tuesday, May 238:45 - 9:00 Opening remarks Room Smith Center xxDan Bernsteine, President, Portland State University Dan Hammerstrom, Chair of ECE Department at Oregon Graduate Institute, M. Perkowski, Symposium Chair
Session 1: Invited address Room Smith Center xx Chair: Y. Hata
9:00 - 10:00 Neural and Fuzzy Computing
J. Zurada, Fife Professor of Electrical Engineering, Head of Computational Intelligence Group, University of Louisville, USA
10:00 - 10:30 Refreshment break Session 2a: Logic and Algebra I Room Smith Center xx Chair: I. Rosenberg
10:30 - 11:00 The 2-SAT Problem of Regular Signed CNF Formulas
B. Beckert, R. Haenhle, University of Karlsrue, Germany Felip Manya, Universitat de Lleida, Spain
11:00 - 11:30 Finite-Valued Approximation of Product Logic
S. Aguzzoli, Istituto per la Ricerca Scientifica e Tecnologica, Italy, B. Gerla, University of Milan, Italy
11:30 - 12:00 Integration of Information in Four-Valued Logics under Non-Uniform Assumption
Y. Loyer, N. Spyratos, D. Stamate, Laboratorie de Recherche en Informatique, France
Session 2b: Reed-Muller Logic Room Smith Center 00-010 and Its Extensions Chair: R. Stankovic
10:30 - 11:00 Fast Transforms for Multiple-Valued Input Binary Output PLI Logic
B. J. Falkowski and S. Rahardja, ???? Singapure
11:00 - 11:30 Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams
H. M. H. Babu and T. Sasao, Kyushu University??, Japan.
11:30 - 12:00 A New Algorithm to Compute Quaternary Reed-Muller Expansions
S. Rahardja and B.J. Falkowski, ???? Singapure
12:00 - 13:30 Lunch (Executive Subcommittee Meeting) Session 3: Invited Address Room Smith Center xx Chair:
13:30 - 14:30 Dan Hammerstrom
14:30 - 14:45 Refreshment break Session 4a: Decomposition and Data Mining Room Smith Center xx Chair: J. Muzio
14:45 - 15:15 Multi-Valued Sub-functions Encoding in Functional Decomposition Based on Information Relationship Measure
A. Chojnacki, and L. Jozwiak, Eindhoven University of Technology, Faculty of Electrical Engineering
15:15 - 15:45 Data Mining of Weak Functional Decomposition
S. Jaroszewicz, and D. Simovici University of Massachusetts at Boston, Dept. of Math. and Comp. Sci.
Session 4b: Spectral Approaches in Image Processing, Fault Analysis and Logic Synthesis Room Smith Center 00-010 Chair: C. Moraga
14:45 - 15:15 Gray Scale Image Compression Based on Multiple-Valued Input Binary Functions, Walsh and Reed-Muller Spectra
B.J. Falkowski and L. S. Lim, ????? Singapur
15:15 - 15:45 Fault Analysis of the Multiple-Valued Logic using Spectral Method
J. O. Kim, Y. G. Kim and H. S. Kim
15:45 - 16:15 Computation of Spectral Information from Boolean Netlist
R. Drechsler, Alberts-Ludwigs University, Institute of Computer Science, Germany, M. A. Thornton, ECE Dept., Mississippi State University
16:15 - 16:30 Refreshment break Session 5a: Verification and Analysis Room Smith Center xx Chair: G. Pogosyan
16:30 - 17:00 Probabilistic verification of Multiple-Valued Functions
E. Dubrova, Royal Institute of Technology, Department of Electronics, Sweden Harald Sack, University of Trier, Germany
17:00 - 17:30 A Method for Approximate Equivalence Checking
M. Thornton, ECE Dept., Mississippi State University, USA R. Drechsler, W. Guenther, Alberts-Ludwigs University, Institute of Computer Science, Germany
17:30 - 18:00 Propagation algorithm of behavior probability in power estimation based on multiple-valued logic
X. Wu and M. Pedram, ???
Session 5b: Algebra Room Smith Center 00-010 Chair: R. Haehnle
16:30 - 17:00 Rigidity problems of autodual clones
M. Miyakawa and I. G. Rosenberg ?????????
17:00 - 17:30 Some Properties of Discrete Interval Truth Values Logic
N. Takagi and K. Nakashima ???????????
17:30 - 18:00 On Urguhart's C Logic
A.Ciabattoni, University of Milano, Dipartimento di Informatica, Italy 18:00 Excursion to Intel
Wednesday, May 24 Session 6: Invited Address Room Smith Center xx Chair: E. Dubrova
9:00 - 10:00 Analog Evolvable Hardware for Space Applications
A. Stoica, NASA, Pasadena, CA, USA.
10:00 - 10:15 Refreshment break Session 7a: Decision Diagrams Room Smith Center xx Chair: R. Drechsler
10:15 - 10:45 Lower Bound Sifting for MDDs
D. Jankovic, W. Guenther, R. Drechsler Albert-Ludwigs-University, Institute of Computer Science, Germany
10:45 - 11:15 Implementation of Multiple-Outputs Functions using PQMDDs
Y. Iguchi, T. Sasao and M. Matsuura, ????
11:15 - 11:45 Fibonacci Decision Diagrams and Fibonacci Spectral Decision Diagrams
S. Stankovic, M. Stankovic, University of Nis, Yugoslavia J.T. Astola, K. Egiazairan, Int. Center for Signal Processing, Tampere Univ. of Technology, Tampere, Finland
11:45 - 12:15 Mod-p Decision Diagrams: A Data Structure for Multiple-Valued Functions
H. Sack, University of Trier, Germany, E. Dubrova, Royal Institute of Technology, Department of Electronics, Sweden, Ch. Meinel, University of Trier, Germany
12:15 - 12:45 Dynamic Re-Encoding During MDD Minimization
F.Schmiedle, W.Guenther, R.Drechsler Alberts-Ludwigs University, Institute of Computer Science, Germany
Session 7b: Fuzzy Logic Room Smith Center 00-010 Chair: Mukaidono
10:15 - 10:45 Fuzzy Decision Diagrams for the Presentation of Rule Bases
K. Strehl, C. Moraga, and K.-H.Temme, Universitat Dortmund, Germany, R. S. Stankovic, University of Nis, Yugoslavia
10:45 - 11:15 A New Class of Fuzzy Modifiers
M.DeCock, E.Kerre Department of Applied Mathematics and Computer science, Faculty of Sciences, Universiteit Gent, Belgium H. Thiele, Universitat Dortmund, Germany
11:15 - 11:45 On Algebraic Formulation of Information Granulation III,
Investigation the Hata-Mukaidono Approach H. Thiele, Universitat Dortmund, Germany 11:45 - 13:00 Lunch (Symposium Subcommittee Meeting)
Session 8a: Circuits Room Smith Center xx Chair: M. Kameyama
13:00 - 13:30 Cost-Analysis of 4-Valued Unary Functions
Implemented using Current-Mode CMOS Circuits M. Abd-El-Barr and A. Al-Mutawa, ???????
13:30 - 14:00 Implementation of Multiple-Valued Multiplier on
GF(3^m) using Current Mode CMOS H. K. Seong, J. S. Choi, B. S. Shin and H. S. Kim
14:00 - 14:30 Novel Pi-Type Resistor Network in D/A Converter based on multiple-valued logic
X. Wu and X. Zhou ?????
14:30 - 14:45 Refreshment break14:45 - 15:15 Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal LevelsT. Hanyu, T. Ike and M. Kameyama ???????Session 8b: Neural and Threshold Circuits Room Smith Center 00-010 Chair: L. Haddad
13:00 - 13:30 Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors
J. Shen, M. Inaba, K. Tanno, and O. Ishizuka ??????????
13:30 - 14:00 The Synthesis of the Multiple-Vlaued Logic Circuits by Using the Local-Excitation-Type Neuron Models
M. Matumoto, Y. Ueda and I. Nomoto
14:00 - 14:30 Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions
M. Syuto, J. Shen, K. Tanno, and O. Ishizuka
14:30 - 14:45 Refreshment break
14:45 - 15:15
Session 9: Invited Address Room Smith Center xx
15:15 - 16:15 Ivan Bratko
16:15 - 17:30 Plenary Session Room Smith Center xx G. Dueck, University of Antigonish, Canada 18:00 Banquet in Pittock Mansion Speaker: Prof. Lee Casperson, IEEE Fellow, OSA Fellow, ECE Dept. Why water animals move their heads. Thursday, May 25 Session 10: Panel Discussion Room 00-036 Chair: R. Drechsler Panelists: J. Muzio, T. Sasao, M. Kameyama, K.C. Smith, M. Perkowski, A. Mishchenko, R. Daasch, industry people. This panel discussion will try to ask and answer some provocative questions: What is MVL? Is there such research area as Multiple-valued logic? Why there are no MVL departments? What are practical uses of MVL? Has anybody done any money on MVL? What is the industrial perception of MVL? Education in MVL. Grants and funding. Books.
9:00 - 10:00 Multiple-Valued Logic: Provocative questions.
10:00 - 10:30 Refreshment break Session 11a: Circuits II Room 00-036 Chair: T. Sasao
10:30 - 11:00 A Novel Multiple-Valued T-Gate using Multiple-Juncion Surface Tunnel Transisters and Its Application to Three-valued Data Flip-Flop
T. Uemura and T. Baba ??????
11:00 - 11:30 A Study on the Ternary Parallel Circuit Design with DCG properties based on the Matrix Equation
G. N. Byun, C. U. Lee, S. Y. Park and H. S. Kim ?????????
11:30 - 12:00 Novel Resonant-Tunneling Multiple-Threshold Logic Circuit Based on Switching Sequence Detection
T. Waho, K. Hattori and K. Honda ?????? Session 11b: Evolutionary and Information Theory Approaches Room Smith Center 00-010 Chair: O. Ishizuka
10:30 - 11:00 Evolutionary Multi-Level Circuit Synthesis in Given Design Style
T. Luba, S. Yanushkevich, M. Opoka, C. Moraga, and V.Shmerko ???????
11:00 - 11:30 An Evolutionary Computing Approach to Multiple-Valued Logic Synthesis with No Restriction of Circuit Structure
T.Hozumi, O. Kakusho and K.Yamato ???????
11:30 - 12:00 Information Theory Approach for Mimimization of Polynomial Expressions over GF(4)
S. N. Yanushkevich, D. V. Popel, V. A. Cheushev, V. P. Shmerko and R. S. Stankovic, ?????? 12:00 - 13:00 Lunch Session 13: Invited Address Chair: 13:00 - 14:00 NOWY: Zwick. mV memory intel, Zadeh, Kacprzyk, Pawlak, Mulawka , Ras, Victor Marek Session 14a: Fundamental Algorithms Room Smith Center 00-010 Chair:
14:00 - 14:30 Chaining Techniques for Automated Theorem Proving in Many-Valued Logics,
H. Ganzinger V.Sofronie-Stokkermans Max-Planck-Institut fuer Informatik, Germany
14:30 - 15:00 On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions
T. Sasao, ??????? Session 14b: Systems Room Smith Center xx Chair:
14:00 - 14:30 Dram-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage,
T. Hanyu, H. Kimura and M. Kameyama ???????
14:30 - 15:00 An Efficient Data Transmission Technique for VLSI Systems based on Multiple-Valued Code-Division Multiple Access
Y. Yuminaka, O, Katoh, Y. Sasaki, T. Aoki, and T. Higuchi, ?????
15:00 - 15:30 Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic
S. Kaeriyama, T. Hanyu and M. Kameyama 15:30 - 15:45 Refreshment break Session 15: Invited Address Room Smith Center xx Chair: 15:45 - 16:45 japoniec 16:45 - 17:00 Refreshment break Session 14a: Algebra Room Smith Center xx Chair:
17:00 - 17:30 Clarifying the Axioms of Boolean Algebra based on the Method of Indeterminate Coefficients
T. Ninomiya and M.Mukaidono
17:30 - 18:00 Logic Synthesis of Controllers for B-ternary Asynchronous Systems,
Y. Nagata, D. M. Miller and M. Mukaidono ??????????? Session 14b: Arithmetic Room Smith Center 100 Chair:
17:00 - 17:30 High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables
T.Aoki, K. Nakazawa and T.Higuchi ???????? 18:00 Closing remarks Room Smith Center xx ULSI Workshop Friday, May 26 10:00 - 10:20 Registration 10:20 - 10:30 Opening remarks Room PCAT 138 Takao Waho, Workshop Organizer Session 1: Room PCAT 138 Chair: 10:30 - 11:15 11:15 - 12:00 12:00 - 13:00 Lunch Session 2: Room PCAT 138 Chair: 13:00 - 13:45 13:20 - 13:40 13:40 - 14:00 14:00 - 14:20 14:20 - 14:40 Refreshment break Session 3: Room PCAT 138 Chair: 14:40 - 15:20 15:20 - 16:00 15:40 - 16:00 16:00 - 16:20 Session 4: Chair: 16:20 - 16:40 16:40 - 17:00 17:00 - 17:20 17:20 - 17:40 Tuesday, May 23 Notes Map Posters Software and Classwork Demos