The 9th International Workshop on Post-Binary Ultra-Large-Scale-Integration (ULSI) Systems will be held on Friday, May 26, from 9 a.m. to 3 p.m., at the same site as the ISMVL2000. In this workshop, emphasis is placed on the technological aspects of MVL.

The MVL scheme has exhibited several advantages in arithmetic operations, data communications, signal processing, and so on. Real challenges are what to do to implement it on a semiconductor wafer. MV memory chips were developed recently; will the logic circuits follow them near future? As the sub-0.1u ULSI age is coming, it is a good time to overview the present MVL technology and to talk about the future ULSI paradigm that would break the limit of conventional binary LSIs.

The workshop includes the invited lecture by Prof. Mazumder with the University of Michigan, and five papers describing state-of-the-art research results.

I believe all participants will enjoy them. Please feel free to join us!

• Post-binary LSI systems: Present status and future challenges

  Pinaki Mazumder, University of Michigan, USA

  
  

• Beyond-Binary Arithmetic Algorithms and Implementations

  Takafumi Aoki and Tatsuo Higuchi, Tohoku University, Japan

  
  

• Multiple-valued Threshold Logic: Past, present and future

  Claudio Moraga, University of Dortmund, Germany

  
  

• Multiple-Valued Logic-in-Memory VLSI and Its Application

  Takahiro Hanyu and Michitaka Kameyama, Tohoku University, Japan

  
  

• Development of Negative Differential Resistance (NDR) Devices for Multiple-valued

  Circuit Application

  T. Uemura, NEC, Japan

  
  

• Neuron-MOS Multiple-Valued Logic Circuits

  Koichi Tanno, Miyazaki University, Japan

If you have any questions, please contact Workshop Organizer, Takao Waho (waho@sscd.ee.sophia.ac.jp), Sophia University, Japan.