Glossary of Test, Design for Test, Fault Models, Test Equipment, and Verification.
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Glossary
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- ACE
-
ASIC Compiler Environment. The graphical user interface delivery mechanism
for submicron gate-array memory compiler elements.
(TI*)
- ACCELERATED BURN-IN TEST
-
Same as burn-in test, but executed in a higher temperature (nominally at 150 degrees of Celcius)
but in a shorter period of time.
(PER*)
- ACCEPT NUMBER
-
The maximum number of devices that may fail a sample test without causing rejection of the lot.
For Military Products, that number is zero.
(TI*)
- ACCEPTABLE QUALITY LEVEL (AQL)
-
A hypergometric sampling plan defined as the
interpolated percent defective for which there is a 95% probability of acceptance
under the plan to the specified maximum percent defective.
(TI*)
There is a 95% confidence that
material of the stated AQL will pass sample inspection. This is
distinct from reliability, which measures failures over an extended period of time.
(PER_SM*)
- AQL
-
See Acceptable quality level.
(PER*)
- ALIASING
-
whenever the faulty output produces the same signature as a fault-free output.
(SR*)
- ANALOG
-
A signal in an electronic circuit that takes on
a continuous range of values rather than only a few discrete values; a
circuit or system that processes analog signals.
(SM*)
- ANALYSIS
-
See under Verification.
(PER*)
- APPLICATION-LEVEL SYNTHESIS
-
Synthesis from specifications described in a style natural to an application area such
as dataflow diagrams for DSP applications.
(SM*)
- APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
-
The common name for semi-custom integrated cicuits. These can include digital, linear, and mixed-level circuits.
(TI*)
- ASIC COMPILER ENVIRONMENT (ACE)
-
The graphical user interface delivery mechanism for submicron gate-array memory compiler elements.
(TI*)
- ASIC TDL 91
-
An improved TI TDL format that supports both narrow and wide (SCAN)
TDL. Narrow TDL lists the ATE state for all pins in every cycle. Wide or SCAN
TDL allows a description of only nonredundant ATE states and pins.
(TI*)
- ASPECT RATIO (MICROPATTERNING)
-
In etch, the depth-to-width ratio of an opening on a wafer. In feature profile,
the ratio of height to width of a feature.[1]
(SM*)
- AUTOMATED TEST EQUIPMENT (ATE)
-
Automated test equipment used to perform electrical testing of integrated circuits.
(PER*)
- ATPG
-
See Automatic test pattern generation.
(PER*)
- AT-SPEED TEST
-
Any test performed on an IC that tests the device at its normal operating clock frequency.
(PER*)
- ATTRIBUTES DATA
-
Quantitative data indicating the total number of
devices subjected to and passing or failing the various screening steps in a test sequence.
(TI*)
- AUTOGEN
-
A TI software tool that compiles an automated test equipment (ATE)
program from TDL.
(TI*)
- AUTOMATIC TEST PATTERN GENERATION (ATPG)
-
A process by which the vectors requiredto produce a high-fault
coverage for a design are generated by a program.
These tools generally require scans in synchronous designs and assume certain scan rules.
(TI*)
- AUTOMATIC FLOW CONTROL
-
Full automatic operation of CHIPS including expansion
and clustering of the netlist, specification of base-array and I/O locations,
and floorplan generation. Recommended on first pass through CHIPS to uncover
potential timing problems. Identical to running PRELUDE with the -chipsdb
switch set to true.
(TI*)
- AUTOMATIC PLACEMENT
-
See automatic flow control.
(TI*)
- AUTOMATED SYSTEM TEST
-
Automatic insertion of
testability features at the system level, driven by a high-level
description of the system and identification of appropriate test
methods for each system block.
(SM*)
- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% BBBBBBBBBBBBBBB
- BACK ANNOTATION
-
A process of extracting path delays from a design layout and
transporting them back (generally as pin-to-pin delays) to your timing
verification tools for accurate postlayout timing checks.
(TI*)
- BALUN
-
Transmission line or lumped-element impedance transforming
or BALanced/UNbalanced line matching device.
(TI*)
- BASE ARRAY
-
A partially manufactured array containing unconnected transistors.
The array has a periphery to locate interface buffers and a core composed of
base cells for implementing the logic. The architecture of the core is a very
dense sea-of-gates. Wafer banks of the base arrays are kept in inventory
awaiting metallization to program and interconnect the transistors to make an
ASIC.
(TI*)
- BASEBAR
-
TI terminology for base array or the TI library containing base arrays.
(TI*)
- BARE DIE
-
Individual, unpackaged silicon integrated circuits.
(SM*)
- BASIC CELL
-
The smallest physical area on an ASIC array repeated in both the X
and Y directions to populate the core matrix. Contains unconnected components
that can be programmed individually or in groups to form macros of varying
complexity.
(TI*)
- BEHAVIORAL
-
A level of logic design that involves
describing a system at a level of abstraction that does not involve
detailed circuit elements, but instead expresses the circuit
functionality linguistically or as equations.
(SM*)
- BENCHMARKS
-
Standard circuits or tests that can be used
to compare the performance of software programs or tools. Each program
or tool is applied to the benchmark circuit and the results compared.
(SM*)
%BEEEEEE
- BEST COMMERCIAL PRACTICES (BCP)
-
A way of optimizing processes, procedures,
and organizations to provide more accessible systems and products for customers, the DOD, and IC manufacturers.
(TI*)
- BIT-PLANE ORGANIZATION
-
Each location in memory represents (N)
number of bits with each bit representing the same color plane.
(TI*)
- BIST
-
See Built-in self test.
(PER*)
- BLOCK
-
A group of cells interconnected together that may contain hierarchically other blocks.
(PER*)
- BLOCK LEVEL
-
A high-level architectural schematic of a
system or function that hides detail and displays a collection of
circuit elements as a single block.
(SM*)
- BOND PULL
-
Pulling of the bond wires to destruction
to determine the strength of the bonds as defined in MIL-STD-883, Test Method 2011.
(TI*)
- BOUNDARY SCAN
-
A scan path that allows the I/O pads of an IC to be both controlled and observed.
(SM*)
- BRIDGING FAULT
-
A fault modeled as a short-circuit between two nets on a chip.
(SM*)
- BUILT IN SELF TEST (BIST)
-
The capability of a product to carry out a functional
test of itself. Some support from external equipment may be required. BIST
usually involves special hardware in the product to generate input stimuli and
to analyze test responses.
(TI*)
Methods of testing an IC
that use special circuits designed into the IC. This circuitry then
performs test functions on the IC and signals whether the parts of the
IC covered by the BIST circuits are working properly.
(SM*)
built-in self-test (BIST): the inclusion of on-chip circuitry to provide testing .
(SR*)
- BURN-IN
-
A screening operation subjecting devices to high temperature bias
(commonly at 125 degree celcius) for 160 hours.
(TI*)
The process of exercising an integrated circuit
at elevated voltage and temperature. This process accelerates failure
normally seen as "infant mortality" in a chip. The resultant
tested product is of high quality.
(SM*)
% CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC
- CADENCE
-
Trademark of Cadence Design Systems, Inc. Refers to any of the products
marketed by this company.
(TI*)
- CADENCE DATABASE ACCESS (CDBA)
-
Files used for synthesis and schematic capture with the Cadence toolset.
(TI*)
- CAD VIEW
-
Computer Aided Design view. A unique CAD representation of a full or
partial design. For example, a sub-block within your design may have a netlist
view corresponding to the design netlist or a symbol view for its capture
system symbol.
(TI*)
- CANTILEVER PROBES
-
Electrical probes for making contact
to bare chips that are constructed with the contacting pad at the end
of a flexible beam.
(SM*)
- CAPTURE
-
A process of describing your design. Generally used to mean building a
gate-level description.
(TI*)
- CD
-
See Critical dimension.
(PER*)
- CD CONTROL
-
See Critical dimension.
(PER*)
- CELL
-
An individual component of a library (typically a logic gate; for example,
a NA210 2-input NAND gate). See macro.
(TI*)
- CELL LIBRARY
-
Contains all of the cells in the appropriate submicron gate-array
macro library summary. All submicron gate-array users receive this library as
part of the release.
(TI*)
- CERTIFICATE OF CONFORMANCE
-
A certificate provided by a manufacturer's QA organization to confirm that all material in that lot conforms to
all applicable specifications.
(TI*)
- CHARACTERIZATION
-
The process of testing an integrated
circuit in sufficient detail to qualify the process by which it was
manufactured and measure the associated process margins. This is
separate from testing, which is done on product for shipment to verify outgoing quality.
(SM*)
- CHEMICAL AMPLIFICATION
-
Used in photolithography to
describe a process in which process exposure sensitivity of a
photoresist is enhanced through secondary chemical reactions that are
triggered by a primary photochemical reaction.
(SM*)
- CHEMICAL MECHANICAL POLISH (CMP)
-
A process for removal
of surface material from a wafer to obtain submicron planarity. The
process uses chemical and mechanical actions to achieve a mirror-like
surface for subsequent processing.[2]
(SM*)
- CIRCUIT DESIGN
-
Techniques used to connect active
(Transistors) and passive (Resistors, Capacitors, and Inductors)
elements in a manner to perform a function (i.e., logic, analog).
(SM*)
- CLASS
-
Per MIL-STD-883, there are two product
assurance classes representing different levels of expected device reliability:
(TI*)
- CLASS B
-
Per MIL-STD-883, there are two processing levels for high reliability microcircuits.
Class B- for unmanned flight applications or high-reliability ground support systems
(TI*)
- CLASS S
Class S- for manned space flight or extrememly high-reliability aerospace applications.
- CLEAN
-
Refers to completion of a specified process without errors. For example,
EDRC clean means that a database has completed Electrical Design Rule Checks
without errors.
(TI*)
- CLOCK FREQUENCY
-
The master frequency of the periodic
pulses that synchronize operations of a logic circuit.
(SM*)
- CLUSTER TOOL
-
An integrated environmentally-isolated
manufacturing system consisting of process, transport, and cassette
modules mechanically linked together. The modules may or may not come from the same supplier.[2]
(SM*)
- CMOS
-
Complementary Metal Oxide Semiconductor.
(TI*)
- COM
-
Commercial. Refers to commercial characterization conditions for library.
(TI*)
- CO-DESIGN FAB
-
See Hardware/Software Co-design.
(SM*)
- COMPLIANT DEVICES
-
Refers to devices processed in accordance with MIL-PRF-38535.
(TI*)
- COMPREHENSIVE HIERARCHIAL
PHYSICAL SYNTHESIS (CHIPS)
-
TI's submicron gate-array
floorplanning tool designed to improve design cycle time by decreasing layout
iterations. Includes PRELUDE delay estimation capabilities plus full graphic
floorplanning.
(TI*)
- COMMAND LINE
-
A command consisting of program name, followed by zero or more
switches and their respective parameters.
(TI*)
- COMPILER CELL LIBRARY
-
Contains one or more compiler cells.
(TI*)
- CONCURRENCE
-
In the design process allows for multiple
applications (say a floor-planner and a timing analysis application) to
operate on the design within the same active session. Incremental
processing is the art of performing design analysis only on the
changed portion of the design (thus the processing time is proportional
to the size of the design change and not the entire design).
(SM*)
- CONFOCAL
-
A microscope design with superior abilities to image submicron features on a wafer.
(SM*)
- CONJUGATE BRIDGE
-
The detector circuit and the supply
circuit are interchanged as compared with a normal bridge of the given
type.[3]
(SM*)
- CONTROLLABILITY
-
The ability to control an individual circuit during testing.
(SM*)
- COO
-
See Cost of ownership.
(PER*)
- COPLANARITY
-
On a silicon wafer, the condition wherein
all features are polished so their surfaces are in the same plane. In a
leadframe, the total indicator reading (TIR) of the position of all the
tips of the bonding fingers in the Z direction. On the package, the
deviation of the tips of the package terminals from the seating plane of
a surface-mounted package.[2], [3]
(SM*)
- COST OF OWNERSHIP (COO)
-
Total lifetime cost associated
with acquisition, installation, and operation of fabrication equipment.
(SM*)
- CP FAB
-
See Process capability.
(PER*)
- CPK
-
See Process capability index.
(PER*)
- CRITICAL DIMENSION (CD)
-
The width of a patterned line
or the distance between two lines, monitored to maintain device
performance consistency; that dimension of a specified geometry that
must be within design tolerances.[4]
(SM*)
- CORE LIBRARY
-
TI's standard gate array library. Contains all of the cells in the
appropriate submicron gate array macro library summary. All submicron gate
array users receive this library as part of the submicron gate array release.
The library is accessed by the TI_LIB_DIR environment variable.
(TI*)
- CROSSCUT TECHNOLOGIES
-
In the categorization of
technologies, specific technologies that are required by several of the
primary technologies identified in the Roadmap. For example, in this
Roadmap, metrology is a common need of all the primary technologies
required for integrated circuits, thus metrology is a crosscut technology.
(SM*)
- CROSSTALK
-
The undesirable addition of one signal to
another in a circuit usually caused by coupling through parasitic
elements. An example would be inductive or capacitive coupling between
adjacent conductors.
(SM*)
- CUSTOMER DESIGN CENTER
-
Texas Instruments Customer Design Center. Your first
line of support for questions or problems arising with your TI submicron
gate-array design flow.
(TI*)
- CUSTOM LIBRARY
-
Contains one or more cells not included in the standard TI
(core) library, typically a custom macro cell TI specifically supplies for your
design (for example, a custom Boolean function or custom memory). A compiler
cell GOOD library is included with designs using compiler cells.
(TI*)
% DDDDDDDDDDDDDDDDDDDDDDDDDDD
- DAMASCENE
-
An IC process by which a metal conductor
pattern is embedded in a dielectric film on the silicon substrate. The
result is a planar interconnection layer. The creation of a Damascene
structure most often involves chemical mechanical polishing of a
non-planar surface resulting from multiple process steps. A Damascene
trench is a filled trench.
(SM*)
- DATA CONVERSION
-
The changing of data from one format to
a different but equivalent format to allow its use in a different
computer-aided design application.
(SM*)
- DATA INTEGRATION
-
The means by which design data is
transferred between computer-aided design applications.
(SM*)
- DATA MANAGEMENT
-
The organization and control of design
data (files or records) so as to assure proper security, integrity, and
availability of the data.
(SM*)
- DATE CODE
-
The first two digits (or first digit of 3-digit
code) identify the year, the last two digits identify the week.
Normally, the date code is based upon week of seal for the first sublot of the inspection lot.
(TI*)
- DC TEST
-
A sequence of direct current measurements
performed on IC pads to determine probe contact, leakage currents,
voltage levels on inputs and outputs, power supply currents, etc.
(SM*)
- DEFENSE ELECTRONICS SUPPLY COMMAND (DESC)
-
Replaced by DSCC.
(TI*)
- DEFENSE SUPPLY CENTER, COLUMBUS (DSCC)
-
The responsible agency for MIL-PRF-38535 documentation
and qualification relative to QML listing. DSCC conducts Class B line-certification audits.
(TI*)
- DEFECT/FAULT
-
A defect is any physical
abnormality in an IC. A fault is any abnormality in the logical
functioning of a chip. A defect may or may not result in a fault.
(SM*)
- DEFECT LEVEL
-
The number of chips in parts-per-million
that are shipped to customers, and that are defective even though the
test program declares them to be good.
(SM*)
- DELAY FAULT
-
A fault that has the effect of causing a
signal to appear late in arriving at a destination.
(SM*)
- DESIGN
-
A complete ASIC design including I/O buffers. Has a TI-assigned design
number (cfxxxxx).
(TI*)
- DESIGN COMPILER
-
Design synthesis tool from SYNOPSYS.
(PER*)
- DESIGN ENVIRONMEMT
-
A collection of specific tools,
hardware, operating systems, methods, assumptions, capabilities, and
procedures used in a design process.
(SM*)
- DESIGN FLOW MANAGEMENT
-
The ability to define a design
process that reflects the flow of applications that must be correctly
traversed before a design can be released to manufacturing.
(SM*)
- DESIGN FOR TESTABILITY (DFT)
-
A strategy to test your ASIC defined at the start
of the design process rather than at the end.
(TI*)
- DESIGN HANDOFF CHECKLIST
-
A TI-supplied checklist to be completed at design
handoff. Helps you determine whether you have fully met TI's design handoff
requirements. Includes all non-automated handoff checks and complements
automated checks.
(TI*)
- DESIGN METHODOLOGY
-
A comprehensive set of specific
engineering rules, methods, and procedures that are used to design and
implement ICs, subsystems, or systems.
(SM*)
- DESIGN PROCESS
-
The flow between computer-aided design
applications from a user perspective. In today's systems this flow
tends to be sequential with each application processing the entire
design model, and, when complete, the changed design model is then
processed by the next (sequential) application within the design process.
(SM*)
- DESIGN REPRESENTATION
-
A collection of data in specific
formats used to completely characterize a design at a specific level of abstraction.
(SM*)
- DESIGN REUSE
-
Applying elements of an existing design to the solution of a new problem.
(SM*)
- DESIGN RULES
-
Rules that state the allowable dimensions
of features used in the design and layout of integrated circuits; rules
unique to a specific process technology (including limits for feature
size, feature separation, layer-to-layer overlap, and layer-to-layer
feature separation).[1]
(SM*)
- DESIGN RULE CHECK
-
Checking that a specific IC design
complies with the constraints imposed by the specific technology to be
used for its manufacture.
(SM*)
- DESIGN SPACE
-
The set of possible designs and design
parameters that meet a specific product requirement. Exploring design
space means evaluating the various design options possible with a given
technology and optimizing with respect to specific constraints like power or cost.
(SM*)
- DESIGN SPECIFICATION
-
Generated by SPECCAP summarizing design GOOD, TDL GOOD,
and customer information required to manufacture an ASIC. The specification may
be a preliminary document, a prototype document, or a final document. The
prototype and final document types require customer sign-off.
(TI*)
- DESIGN TOOLS
-
Software tools used to complete the design
of IC (or other functions). The collection of all tools required to
complete the design of an integrated circuit.
(SM*)
- DESIGN VERIFICATION
-
The process of verifying the functional and performance requirements
of the design by comparing its operation to its specification.
(PER*)
- DESIGN VERIFICATION TDL
-
The TDL files containing the test vectors used for design verification.
(TI*)
- DETECTOR
-
An electrical design rule checking program that performs core and I/O
checks on a design GOOD. Can also perform package, base array, and testability
checks on a complete design.
(TI*)
- DIAGNOSIS
-
The detection of the cause of a failure in a
system through specialized search techniques.
(SM*)
- DIE SORT
-
See Wafer sort. (PER*)
- DIGITAL
-
A signal used to transmit information that has
only discrete levels (usually 2) of some parameter (usually voltage) (See Analog.).
(SM*)
- DIRECT WRITE
-
A method of pattern transfer in which the
elements comprising the pattern are formed serially rather than
simultaneously through a mask, e.g., employing an electron beam to form
an IC process pattern by scanning the beam across the resist layer
while turning it on and off.
(SM*)
- DOUBLE-LEVEL METAL (DLM)
-
Double-Level Metal. An interconnect technology with two levels of metal.
(TI*)
- DSCC STANDARD MICROCIRCUIT DRAWING (SMD)
-
A second level of part standardization
(first level is 38510) with detailed identification of electrical performance requirements.
(TI*)
% EEEEEEEEEEEEEEEEEEEEE
- E-BEAM LITHOGRAPHY
-
Electron-beam Lithography
(TI*)
- EDGE EXCLUSION
-
Wafer layout in which the periphery of
the wafer is not used in recognition of the low yields obtained there.
(SM*)
- EDIF2GOOD
-
A netlist translator program that builds a design GOOD from an EDIF
2.0 netlist.
(TI*)
- ECO
-
A CHIPS feature used to make minor and valid
changes to a netlist. Requires clustering the new netlist to look like the
original one, placement of all components as in the old floorplan, and
resolving the hierarchical location and floorplan placement of new instances
not part of the original netlist.
(TI*)
- ELECTRONIC DESIGN DATABASE MODEL (EDDM)
-
A database used by Mentor for schematic
capture and synthesis.
(TI*)
- ELECTRONIC DESING INTERCHANGE FORMAT (EDIF)
-
A textual language designed to allow
all forms of electronic design information transfer between different CAD
systems. Currently implemented for netlist and schematic circuit descriptions,
although there are significant differences between different tool vendor
implementations (which may impair portability).
(TI*)
- ELECTRICAL DESIGN RULE CHECKING(EDRC)
-
The process of checking your gate-level
design implementation against technology, packaging, and testability design
rules. DETECTOR is the submicron gate-array EDRC tool.
(TI*)
- ELECTROSTATIC DISCHARGE
-
The discharge of accumulated static charge (typically of high
voltage at low current) from one collector to another, usually by jumping the air
gap between the two collectors.
(TI*)
- ELECTROMIGRATION (EMG)
-
The self-diffusion of aluminum
along interconnects caused by the current flow through the aluminum.[1]
(SM*)
- EMG
-
See Electromigration. (PER*)
- EMULATION
-
See under Verification.
(PER*)
- ESTIMATOR
-
A program or operator which, when applied to
a system or circuit representation, can obtain an estimate of some
parameter or value, e.g., power, speed, or manufacturing yield.
(SM*)
- EVENT STREAM OUTPUT (ESO)
-
A binary representation of the IKOS print-on-change
(POC) file format.
(TI*)
- EXTRACTION
-
The generation of a set of values for
desired parameters based on the analysis of a design representation.
For example, the generation of a transistor net list or a set of
parasitic capacitances and resistances from the detailed layout
representation of an IC.
(SM*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% FFFFFFFFFFFFFFFFFFFF
- FACTORY INTEGRATION
-
The coordination of all of the
elements required to successfully operate a factory, i.e., product
definition, human factors, material flow, equipment scheduling/control,
environmental controls, and facilities.
(SM*)
- FAILURE IN TIME (FIT)
-
Number of failures per billion device operating hours.
Calculated based on actual life test data and usually derated to 55 degrees
centigrade within a specific confidence level. per billion device operating hours.
(TI*)
- FAULT
-
See Defect.
(PER*)
- FAULT COVERAGE
-
The percentage of a particular fault
type that a test vector set will detect when applied to a chip.
(SM*)
fault coverage: the fraction of possible failures that the test technique can detect.
(SR*)
- FAULT DICTIONARY
-
A list of faults that a test vector
will detect in a failing circuit. A list of all such faults for each
vector in a vector set.
(SM*)
- FAULT GRADE
-
A measurement of the efficiency of test vectors to detect
manufacturing defects in silicon. The fault-grade value is usually presented as
a percentage of the stuck-at faults that can be identified using those test
vectors.
(TI*)
- FAULT MODEL
-
(i.e., Stuck-at, Timing, Bridging, Etc.): A
model of the behavior of defective circuitry in an IC. Physical defects
result in improper behavior in a circuit which must be modeled in order
for test patterns to be designed to properly detect them.
(SM*)
- FAULT SIMULATION
-
A simulation of a chip with a given
set of test vectors with the expresses purpose of determining the
extent to which the given test vectors detect a specific type of fault.
(SM*)
fault simulation: an empirical method used to determine how faults
affect the operation of the circuit and also how much testing is required to
obtain the desired fault coverage.
(SR*)
- FINE LEAK
-
Hermeticity testing performed on ceramic packages for
low level leakage rates as defined in MIL-STD-883, Test Method 1014.
(TI*)
- FIZZ2GOOD
-
Physical to GOOD. An annotation program that writes voltage,
temperature, package, tester, design-port to package-pin mapping information,
and user timing constraints into the design GOOD.
(TI*)
- FLASH MEMORY
-
A non-volatile semiconductor memory
consisting of 1-transistor cells wherein charge storage in the gate
dielectric is the memory mechanism and a second gate on the transistor
enables serial insertion of data and simultaneous erasure of defined
blocks of memory electronically.
(SM*)
- FLOORPLAN
-
1) The CHIPS/PRELUDE physical design hierarchy. 2) The CHIPS/PRELUDE
function that invokes the interactive floorplanning and delay estimation tools.
(TI*)
- FLOOR PLANNING
-
The act of determining a physical layout
of an IC from information contained in a netlist and a library of the
physical characteristics of individual cells contained in the netlist.
The purpose of floor planning is to obtain a physical layout that is
acceptable in terms of system requirements, such as area, clock speed,
power, and signal integrity.
(SM*)
- FLOW
-
A series of connected processes performing a useful operation (for
example, Verilog flow or Mentor flow).
(TI*)
- FORMAL METHODS
-
Rigorous, discrete mathematical approach
for the process of specifying, designing and verifying circuits and systems.
(SM*)
- FORWARD ANNOTATION
-
The addition of data to a design GOOD to influence
subsequent steps in the design flow. In the submicron gate-array design flow it
is possible to forward annotate timing constraints to layout.
(TI*)
- FRAMEWORK
-
A software system used to interconnect
individual design tools, and that allows all of the design tools
necessary to complete an IC design to be properly and effectively
linked together.
(SM*)
- FUNCTIONAL TEST
-
One or more tests to determine whether
a circuit's logic behavior is correct.
(SM*)
% GGGGGGGGGGGGGGGGGGGGGG
- GATE COUNT
-
A measure of the size of an ASIC design, usually expressed in terms
of the equivalent number of basic 2-input NAND gates used.
(TI*)
- GATE ENSEMBLE (TM)
-
A Cadence tool for automatic place and route of sea-of-gates
arrays. Used by TI for fully automated layout of all submicron gate-array
designs. Accepts forward-annotated timing constraints to influence layout.
(TI*)
- GENERIC DATA
-
Data pertaining to a device/package family, not necessarily on a specific part but representative of it.
Group C and D generic data can be supplied in lieu of qualification or quality conformamce when applicable.
(TI*)
- GENERIC ACCESS PORT (GTAP)
-
A TI ASIC test port that allows PMT and other
ASIC tests to be executed from a common test port.
- GLASS-FRIT SEAL
-
A seal that is made by melting and rehardening a glass seal ring between the package base and the lid.
(TI*)
- GETTERING
-
A controlled modification of the silicon
crystal to draw impurities to the bulk, or to the back surface of the
wafer. Contaminants are removed sufficiently far from the front
surface, where the devices are built, to render their potential
degrading effects negligible.[1]
(SM*)
- GLOBAL USER INTERFACE
-
A standard user interface for all TIDSS tools. It defines
how programs should interact with the user (input, output, options, switches,
error output, error handling, etc.).
(TI*)
- GOOD
-
Generic Object Oriented Database. A database structure used to store
design and library information.
(TI*)
- GOOD2CSDF
-
A program that provides back annotation for Verilog and VHDL (VSS and
LeapFrog) simulators. Reads prelayout or postlayout timing from a design GOOD
and writes an OVI standard delay format (SDF) file.
(TI*)
- GOOD2IKOS
-
A program that extracts netlist, internal timing, and design
interface data from GOOD for prelayout and postlayout simulation on IKOS.
(TI*)
- GOOD2MSDF
-
A program that provides back annotation for QuickSim II simulator.
Reads prelayout or postlayout timing information from a design GOOD and writes
a Mentor standard delay file.
(TI*)
- GOOD2NETCAP
-
A program that generates net capacitance values for annotation into
Synopsys. Reads prelayout or postlayout timing information from GOOD and writes
a file readable by Synopsys' set_load command.
(TI*)
- GRID GENERATION
-
In simulation, the creation of an
ordered set of points in parameter space for which calculated results
will be obtained. The grid structure is important. A coarse grid
results in faster computation at the expense of accuracy and resolution.
A fine grid increases computation requirements while providing greater
accuracy and resolution.
(SM*)
- GROSS LEAK
-
Hermeticity testing performed on ceramic packages for
high level leakage rates as defined in MIL-STD-883, Test Method 1014.
(TI*)
- GROUP A
-
Electrical test sampling performed on each lot.
(TI*)
- GROUPING
-
The process of creating a separate block in the CHIPS/PRELUDE
hierarchy containing specified components placed with all other clusters during
floorplanning. The cell groups are annotated into GOOD by FIZZ2GOOD and read by
CHIPS/PRELUDE during clustering.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% HHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
- HANDOFF
-
The process of transferring your design database to TI for layout and
prototype fabrication.
(TI*)
- HANDOFF DATABASE
-
A database handed off to TI. Composed of a design GOOD,
complete with package, basebar and ATE data, and TDL pattern sets for
production test. Also includes a design specification, although this may be
supplied after layout (see Chapter 10, Handoff for Layout and Fabrication).
(TI*)
- HARD MACRO
-
A logic function with internal connections that cannot be changed.
Refers to compiler cells rather than standard library cells.
See macro
and soft macro.
(TI*)
- HARDWARE DESCRIPTION LANGUAGE (HDL)
-
Used within TI to denote a proprietary HDL
(this format is not supported in the submicron gate-array design flow for
external customer use).
(TI*)
- HERMETICITY
-
Leak or seal testing on all hermetic packages to confirm seal integrity.
This is done in two steps:fine leak, which looks at leak
rates in the 5x10 -8 cc/sec range, and gross leak, which looks for devices with gross
seal defects (see MIL-STD-883, Method 1014)
(TI*)
- HANDLER
-
Equipment for manipulating packaged ICs during the testing process.
(SM*)
- HARDWARE/SOFTWARE CO-DESIGN
-
A style of system design
that considers whether specific system functions should be realized as
software or as hardware, by analyzing trade-offs between design alternatives.
(SM*)
- HIERARCHICAL DESIGN
-
Concurrent, incremental design (See Design Process.).
(SM*)
- HYDROPHILIC
-
Tending to absorb water; tending to concentrate in the aqueous phase.[3]
(SM*)
- HYDROPHOBIC
-
Tending to repel water; lacking affinity for water.[3]
(SM*)
%%%%%%%%%%%%%% IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
- IDDQ
-
See Static current test.
(SM*)
- IEEE_1149.1 (JTAG)
-
A standard that specifies
requirements and protocols for boundary scan test, including the
boundary scan path, the test access and related options for an IC.
(SM*)
- I/O
-
Input, output, or bidirectional buffer cell used to connect design
interface signals directly to package pins.
(TI*)
- IKOS
-
1)IKOS Systems, Inc. Company that produces and supports the Logic Sim
(fast, hardware accelerated) simulator and the Fault Sim (serial algorithm)
fault simulator. 2) The hardware-accelerated gate-level simulation tool from
IKOS Systems, Inc.
(TI*)
- IKOS2GOOD
-
A netlist translator program that builds a design GOOD from an IKOS
netlist.
(TI*)
- IN SITU
-
Latin for "in original position."
Refers to processing steps or tests that are done without moving the wafer.[1]
(SM*)
- INFRASTRUCTURE
-
The understructure, i.e., the supporting
elements and components. For the semiconductor industry, the service
and material suppliers as well as organizations involved in R&D, in
finance and trade, and in other matters external to the producers of
semiconductors but that are required for the industry to successfully operate.
(SM*)
- INTERACTIVE DESIGN
-
A design environment that
facilitates close interaction between the designer and an automatic tool.
(SM*)
- INTERCONNECT
-
The wiring between elements on a chip, package, or board.
(SM*)
- INTERCONNECT DENSITY
-
The patterns of electrical
conductors that are provided both on and off semiconductor chips to
connect circuit elements and to interface with other system elements,
the number of such conductors that are provided in a 1- or
2-dimensional space per dimension unit. Alternatively, interconnect
density may be defined by the conductor pitch that is the sum of the
conductor width and the space to the next conductor.
(SM*)
- INTERNAL SCAN / INTERNAL PARTIAL SCAN
-
A scan path that includes only internal registers of an IC.
(SM*)
- INTEROPERABILITY
-
The ability of two design tools to
interact through the use of compatible data representations. Also, the
use of different compute-aided design tools to perform the same
function within a given design environment.[1]
(SM*)
- INTERPOSER
-
An electrical interconnection structure used
between a silicon IC chip and package, test jig, or other chip that
enables a reduced contact pad pitch on the chip.
- INTERPOSING RELAY
-
A device which enables the energy in
a high-power circuit to be switched by a low-power control signal.
(SM*)
- I/O PINS
-
Connections to an IC through which go the input and output signals.
(PER*)
- KGD
-
See Known good die.
(PER*)
% JJJJJJJJJJJJJJJJJJJJJ
- JTAG
-
Joint Test Action Group. 1) Committee that established the test access
port (TAP) and boundary-scan architecture defined in IEEE Standard 1149.1-1990.
2) The common name for IEEE Standard 1149.1-1990.
(TI*)
%%%%%%%%%%%KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKkkkk
- KNOWN GOOD DIE (KGD)
-
Fully tested chips [possibly
burned-in] that are ready for bonding into multi-chip modules (MCM).
(SM*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% LLLLLLLLLLLLLLLLLLLLLLLLLLLL
- LAFF
-
LISP Archivable File Format. Created by TI.
(TI*)
- LAYOUT
-
The physical geometry of a circuit or chip.
Also, the process of creating this geometry.
(SM*)
- LEAPFROG
-
A Cadence program suite that provides VHSIC hardware description
language (VHDL) analysis, elaboration, and simulation.
(TI*)
- LIBRARY
-
1)(ASIC library) Set of macros offered by ASIC vendor. Contains hard
macro gates (for example, 2-input NAND gate); can also contain soft macro
functions (for example, `161 counter) for improved design productivity.
2) (CAD tool library) Set of data needed to support the ASIC library on a CAD tool.
Data is packaged in the native library format of the CAD tool.
(TI*)
- LIBRARY EXCHANGE FORMAT (LEF)
-
A trademark of Cadence Design Systems, Inc.
(TI*)
- LID TORQUE
-
A test for the integrity of the seal of a semiconductor
device (usually glass-frit-seal) made by twisting the package and the lid in opposite but parallel directions.
(TI*)
- LFSR
-
A shift register formed by D flip-flops and EXOR gates, chained
together, with a synchronous clock, used either as input pattern generator or
as signature analyzer.
(SER*)
- LOG
-
A Mentor ASCII format used and produced by QuickSim II.
(TI*)
- LOGIC
-
A collection of circuit elements that perform a
function, especially a set of elements that use digital logic and
perform Boolean logic functions
(SM*)
- LOGIC DESIGN
-
Techniques used to connect Logic building
blocks or primitives (i.e., AND Gates, OR Gates, etc.) to perform a
Logical operation (i.e., arithmetic.).
(SM*)
- LONG-WIRE PITCH
-
The sum of the line width and spacing
for conductors that traverse chips on the upper levels of interconnect
to connect blocks of functional structures on ICs.
(SM*)
- LOT TOLERENCE PERCENT DEFECTIVE (LTPD)
-
A single-lot sampling method that statistically ensures
rejection of 90% of all lots having a greater percent defective than the specified LTPD.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
- M2V
-
Mentor to Verilog. A Cadence tool used to translate expanded Mentor 7.0
schematic databases to Verilog netlists.
(TI*)
- MACRO
-
One of a collection of precharacterized logic functions (such as a
flip-flop) comprising a library (for example, the TGC2000 Series gate-array
family). A special case of a block with no hierarchy.
See hard macro
and soft macro.
(TI*)
- MANUFACTURING SPECIFICATION
-
A specification generated by SPECCAP summarizing
design GOOD, cell GOOD, TDL GOOD, tester GOOD, and customer information
required to manufacture an ASIC. The specification may be a preliminary
document, a prototype document, or a final document. This specification does
not require customer sign-off.
(TI*)
- MASS BALANCE
-
The identification and quantization of the
products of a process or reaction to where all of the expected products
are quantitatively accounted for.
(SM*)
- MASTER CONTROL FILE (MCF)
-
The MCF contains the stimulus and timing information
written in a TI-specific format. This format is designed to keep the TDL
vectors within the constraints of the ATE.
(TI*)
- MAX
-
Maximum (worst-case) timing model. Corresponds to maximum temperature,
worst-case process (-3 sigma model), and minimum voltage.
(TI*)
- MCM
-
See Multichip module.
(SM*)
- MEGASONIC
-
A method of cleaning or etching through which
the liquid media being employed is mechanically agitated with frequency
acoustic energy to improve control or accelerate the process.
(SM*)
- MEMBRANE PROBES
-
IC test probes that are built on a
flexible membrane. The membrane, with the probes, is brought into
contact with a wafer through the flexure of the membrane.
(SM*)
- MENTOR
-
Mentor Graphics, Inc.
(PER*)
- METRICS/DESIGN METRICS
-
Measures for the quality,
performance, or productivity of the design process and its component tools.
(SM*)
- MIXED SIGNAL
-
An IC that contains both analog and digital circuit elements.
(SM*)
- MIXED BIST AND SCAN
-
Designer-aided selection of either
BIST or Scan techniques for appropriate blocks in a complex chip, with
high coverage and automatic test access.
(SM*)
- MIL-Q-9858A
-
Quality Program Requirements
(TI*)
- MIL-I-45208
-
Quality Program Requirements
(TI*)
- MIL-STD-973
-
Configuration Control-Engineering Changes
(TI*)
|
- MIL-PRF-38535
-
General performance based specification for manufacturing integrated circuits.
(TI*)
- MIL-STD-785
-
Reliability Program Elements
(TI*)
- MIL-E-5400
-
Electronic Equipment, Airborne (Environment)
(TI*)
- MIL-HDBK-454
-
Workmanship
(TI*)
- MIL-STD-704D
-
Input Power
(TI*)
- MIL-STD-883
-
Test method for screening of ICs and hybrids.
(TI*)
- MIL
-
Abbreviation for military. Refers to military characterization conditions
for library.
(TI*)
- MIL-HDBK-217
-
A norm for predictions of reliability (PER*)
- MIN
-
Minimum (best-case) timing model. Corresponds to minimum temperature,
best-case process (+3 sigma model), and maximum voltage.
(TI*)
- MISR
-
Multiple input LFSR.
(PER*)
- MODELING
-
The act or process of generating an abstract
description of a system to simplify the analysis of the system. The
abstract description must be suitable for use with the appropriate analysis tool.
(SM*)
- MOLECULAR MIGRATION
-
The movement or spread of molecules
of a substance in an environment, over a surface, across an interface,
or through a material due to electrical, thermal, pressure, or
concentration gradients, or to random processes.
(SM*)
- MONTE CARLO
-
Random sampling techniques applied in
computer simulations and modeling to obtain approximate solutions in
problems where exact solutions do not exist.
(SM*)
- MORPHOLOGY
-
The shape and size of a line, an area, or a
volume; the texture or topography of a surface; the habit of a crystal;
the distribution of phases in a system (material). Form may mean any of
these or it may pertain to structure, so it does not have a specific
meaning unless given one.[3]
(SM*)
- MULTICHIP MODULE (MCM)
-
A packaging scheme based on interconnecting multiple bare die on a single substrate.
(SM*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% NNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNN
- NARROW TDL
-
Narrow Test Description Language. TDL which explicitly lists the ATE
state for all physical device pins in every cycle. Requires a large amount of
file storage for large scan designs.
(TI*)
- NAVMAT-P4855-1
-
Design Guidelines
(TI*)
- NC-VERILOG
-
Native Compiled-Code Verilog. Cadence' Verilog simulation system.
(TI*)
- NET DELAY
-
The largest single component-to-component delay on a net. For
example, if the component-to-component delays between two sets of components on
the same net are 2 ns and 4 ns, the net delay will be the larger of the two, or
4 ns.
(TI*)
- NETLIST
-
(ASIC usage) A representation of an ASIC design as a set of library
cells and their interconnections. Frequently, but not necessarily, a text file
or set of text files.
(TI*)
- NOMINAL AVERAGE TIMING MODEL (NOM)
-
Corresponds to room temperature (25° C),
mean process, and standard supply voltage.
(TI*)
- NON RETURN TO ZERO
-
A digital waveform that undergoes only one transition per clock cycle.
(SM*)
- NONDESTRUCTIVE BOND PULL
-
Pull stressing of the wires on a device to a pull
force that is less than the minimum pull force limit given for destructive bond pull
(TI*)
- NON-VALUE ADDED (NVA)
-
Screening that does not improve end quality
or reliability of devices.
(TI*)
- NRZ
-
See Non return to zero.
(SM*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%% OOOOOOOOOOOOOOOOOOOOOO
- OBSERVABILITY
-
The ability to observe internally the state of internal nodes in a circuit.
(SM*)
- OFF-LINE TESTING
-
Testing process carried out while the tested circuit is not in use.
(SER*)
- ON-LINE TESTING
-
Concurrent testing to detect errors while circuit is in operation.
(SER*)
- OPEN VERILOG INTERNATIONAL (OVI)
-
A trademark of Cadence Design Systems, Inc
(TI*)
- OPERATING LIFE TEST
-
Sample test using the same conditions as burn-in,
but usually lasting 1000 hours as defined in MIL-STD-883, Test Method 1005.
(TI*)
- OVERCONSTRAINT
-
Application of an artificially low timing constraint. Used to
prioritize delay reduction on a specified path.
(TI*)
- OVERLAY
-
In lithography, the precision with which
successive masks can be aligned with previous patterns on a silicon wafer.
(SM*)
%%%%%%%%%%%%%%%%%%%%%%%%%% PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP
- PACKED-PIXEL ORGANIZATION
-
Each location in memory represents
(N) number of pixels with each pixel representing all color planes (RGB).
(TI*)
- PARTIAL DESIGN
-
A design block within a complete ASIC design. As such, it does
not have I/O buffers or package, basebar, or tester data associated with it;
there are only core cells in a partial design. Since not all design level
checks are applicable, a relaxed set of electrical design rule checks (core
checks only) should be used in DETECTOR.
(TI*)
- PATH TIMING CONSTRAINT
-
A timing constraint applied across a single logic path
in a design. Includes the intrinsic input-to-output path delay through any cell
in the path. TI supports a single-net path timing constraint.
(TI*)
- PATTERN GENERATION (PG)
-
The stage where an ASIC netlist has completed layout and
is converted into geometric patterns for photomask production.
(TI*)
- PARADIGM
-
An outstandingly clear or typical example.
(SM*)
- PARALLEL MODULE TEST (PMT)
-
A TI test methodology where multiplexers are attached
to the pins of a design module to give direct test access from the package
pins.
(TI*)
- PARASITICS
-
Unwanted circuit components (e.g., capacitors or resistors) present in a design.
(SM*)
- PARTITIONING
-
Dividing a system into suitable subsystems
so that either the design or physical layout of the system can be
realized.
(SM*)
- PARTIAL NETLIST CAPABILITY (PNC)
-
A feature supported by DETECTOR that allows
users to select sub-blocks within a design for verification.
(TI*)
- PARTICLE IMPACT NOISE DETECTION
-
A test used to detect devices containing loose internal particles as defined in MIL-STD-883, Test Method 2020
(TI*)
- PASSIVATION
-
Deposition of a scratch-resistant material,
such as silicon nitride and/or silicon dioxide, to prevent
deterioration of electronic properties caused by water, ions, and other
external contaminants. The final deposition layer in processing.
(SM*)
- PLACEMENT
-
The act of determining the exact position of a logic device on a chip/MCM/board.
(SM*)
- PLANARITY
-
See Coplanarity.
(PER*)
- PLACEMENT RULES
-
User-defined rules forcing a special placement group. Defined
for a given technology library. Can also be defined for a specific netlist.
(TI*)
- POLYCIDE
-
A material formed by reaction of polysilicon
with a metal most often applied in the gate structure of a MOS
transistor when polysilicon gate electrode is reacted with a deposited
refractor metal layer to reduce the electrical resistance of the gate.
(SM*)
- POP_UP_MENU
-
Any menu invoked from anywhere inside a TIDSS window.
(TI*)
- POST-SHRINK
-
A descriptor of performance-enhancing
methods for integrated circuits that will become applicable when the
physical limits of scaling (shrinking the dimensions of the
semiconductor structure) are reached. Also used in reference to the
practice of reducing the dimensions of a given device generation after
it is first introduced.
(SM*)
- POWER MANAGEMENT
-
Design techniques that allow power to
be controlled or reduced to achieve specific design goals. These could
include overall chip dissipation or local affects such as
electromigration or voltage drop.
(SM*)
- PRELAYOUT DELAY ESTIMATION (PLDE)
-
Estimate of interconnect timing and
capacitances used to increase accuracy in timing verification of designs before
committing to layout.
(TI*)
- PRINT ON CHANGE (POC)
-
Print On Change. An ASCII output format produced by IKOS Logic Sim.
(TI*)
- PROBER
-
A piece of hardware that allows a collection of
probes to be brought into contact with the chip on a wafer for the
purpose of testing an IC.
(SM*)
- PROCESS CAPABILITY (Cp)
-
For a process under statistical
process control, the ratio of the tolerance limits (specification
window or upper specification minus the lower specification) of a
process to the natural variation of that process (estimated as six times
the standard deviation of the process output.).[1]
(SM*)
- PRELUDE
-
Prelayout delay estimation program. A submicron gate-array program that
reads the netlist and any user timing constraints from the design GOOD and
updates the design GOOD with estimated net timing.
(TI*)
- PRIMITIVE
-
An instance of a component master and the lowest logic level on a
circuit. Many primitive instances can share the same component master.
(TI*)
- PROCESS
-
A variable that defines the manufacturing process conditions
characterizing a library and cannot be altered by the user.
(TI*)
-
PROCESS CAPABILITY INDEX (Cpk)
-
A measure of process performance similar to process capability, but adjusted for any
variation of the average process output from the stated target value
for the process. In a typical process, Cpk is at best equal to process
capability, but most commonly, it is less than process capability. A
process capability index of at least 1.33 is a desirable objective.[1]
(SM*)
- PROCESS CONTROL
-
The ability to maintain specifications
of product and equipment during the manufacturing operations.[1]
(SM*)
- PROCESS SYNTHESIS
-
The procedure of gathering knowledge
on fabrication processes for semiconductors, organizing this knowledge
into models, applying and combining models to optimize fabrication, and
using the models to identify needs, to direct R&D, and to innovate
both devices and processes. The reduction of process variability is the
major goal.
(SM*)
- PRODUCTION TEST
-
A set of test vectors and a test
program applied via a set of test hardware, and optimized to most
economically determine whether an IC contains manufacturing defects.
(SM*)
- PROXIMITY PRINTING
-
The photoprinting of photomask
patterns by exposure of photosensitive material coated on a supporting
substrate to radiation passing through the photomask which is in the
proximity of, but not in contact with, the photosensitive material
being exposed.
(SM*)
- PRODUCTION TEST
-
The process of verifying that a design, as implemented on
silicon, is correctly manufactured.
(TI*)
- PRODUCTION TEST TDL
-
Production test Test Description Language. A TDL file or
files containing the test vectors used for production test.
(TI*)
- PROXIMITY X-RAY
-
A lithography method using X-ray
radiation through a mask close to, but not touching, the resist coated
surface of a silicon wafer.
(SM*)
- PSEUDO-RANDOM PATTERN GENERATOR
-
Generates a binary sequence of patterns
where the bits appear to be random in the local sense (1 and 0 are equally
likely), but they are repeatable (hence only pseudorandom).
(SER*)
- PULLDOWN MENU
-
Any menu invoked from the menu bar of a TIDSS window.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% QQQQQQQQQQQQQQQQQQQQQQQQQQQQ
- QC SIMULATION
-
Quality Check simulation. Used to verify the integrity of a
design database at design handoff. Checks that netlist and test vectors are
consistent and that handoff TDL for production test meets TI's ATE
requirements.
(TI*)
- QFP
-
See Quad Flat Package.
(SM*)
QM PLAN | Quality Management Plan. |
- QUALIFIED MANUFACTURER'S LIST (QML)
-
A performance based specification (MIL-PRF-38535) that
allows the manufacturer to implement best commercial practices while meeting military performance needs.
(TI*)
- QUALIFIED PARTS LIST
-
A list of those suppliers and/or devices that have
been qualified for a given program, specification, or set of specifications.
(TI*)
- QUALIFICATION TESTING
-
A series of one-time only tests used to determine the reliability and mechanical characteristics of a device.
(TI*)
- QUALITY CONFORMANCE INSPECTION
-
Sample tests performed on a periodic basis that determine conformance
of quality and reliability standards and ensure a continuing level of quality for the device type under test.
(TI*)
- QUICKSLIM II
-
Mentor logic simulator.
(TI*)
- QUAD FLAT PACKAGE (QFP)
-
A plastic or ceramic package
that has leads that project down and away from all four sides of a
square package, typically with gull wing lead configuration.[1]
(SM*)
- QUANTUM DEVICE
-
An electronic device structure whose
properties derive from the wave nature of electrons.
(SM*)
% RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
- RANDOM LOGIC
-
The lowest logic level in a circuit.
See primitive.
(TI*)
- RANDOM TESTING
-
The process of testing using a set of pseudorandomly generated patterns.
(SER*)
- RADIO FREQUENCY (RF)
-
Generally, frequencies high
enough to cause problems with electromagnetic radiation.
(SM*)
- RAMP CYCLE TIME
-
For a newly-assembled semiconductor
manufacturing facility, the period of time required to obtain
commercially acceptable yields of a new device generation.
(SM*)
- RAPID THERMAL PROCESSING (RTP)
-
A process in which a
wafer is heated to a specified temperature for short periods of
time.[1]
(SM*)
- ROUTABILITY
-
The ability to route nets in a design based on available routing
resources.
(TI*)
- REGISTER TRANSFER LEVEL
-
A circuit description
that involves describing the circuit in terms of storage registers and
sequence of transfers of data between the registers.
(SM*)
- RESIST
-
A photosensitive liquid-plastic film applied to the surface of a wafer for micropatterning.[1]
(SM*)
- RETICLE
-
A very flat glass plate that contains the
patterns to be reproduced on a wafer; the image may be equal to or
larger than the final projected image. Typical reticle substrate
material is quartz, and typical magnifications are 10, 5, and 1 times
the final size. The reticle is used in a stepper.[1]
(SM*)
- RETURN TO ZERO
-
A digital waveform that changes twice for one cycle of the clock.
(PER*)
- RF
-
See Radio frequency.
(PER*)
- ROUTING
-
The act of connecting all of the nets in an IC
to the ports of the logic elements. Also, the interconnections of the
components on a chip board.
(SM*)
- RTL
-
See Register transfer level.
(SM*)
- RTP
-
See Rapid thermal processing.
(SM*)
- RZ
-
See Return to zero.
(PER*)
- REGISTER TRANSFER LEVEL (RTL)
-
A subset of behavioral modelling constructs which
can be used to model a circuit at the level of data flowing between a set of
registers. This level of abstraction typically contains little timing
information, except references to a set of clock edges and features.
(TI*)
- RULE OF TEN
-
If one does not find a
failure at a particular stage, then detection at the next stage will cost 10
times as much.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% SSSSSSSSSSSSSSSSSSSSSSSS
- SACRIFICIAL ETCHBACK
-
The practice of cleaning a silicon
wafer surface by oxidizing the surface and completely removing the
oxide layer by etching and thereby removing surface contaminants.
(SM*)
- SCALING
-
The proportional adjustment of the dimensions
of an electronic device while maintaining the electrical properties of
the device; results in a device either larger or smaller than the
unscaled device.[1]
(SM*)
- SCANT2
-
A program that converts ASIC TDL 91 SCAN (wide) TDL to narrow TDL.
(TI*)
- SCOPE
-
System Controllability and Observability Partitioning Environment.
Superset of IEEE Standard 1149.1. In particular, SCOPE cells in library assist
in implementation of Built-In Self-Test (BIST) circuits.
(TI*)
- SEQUENTIAL FAULT
-
A fault that causes a combinational circuit to behave like a sequential one.
(SER*)
- SIMULATION
-
See under Verification.
(SM*)
- SPC
-
See Statistical process control.
(SM*)
- SPEED BINNING
-
The practice of sorting devices at final
electrical test on the basis of performance in a switching speed test.
The variations in performance result from process variances. The
products are given product designations based on operating speed ranges.
(SM*)
- STANDARIZED TEST HARDWARE
-
ATE components that perform
with the same specifications, independent of the test system manufacturer.
(SM*)
- STANDARIZED TEST SOFTWARE
-
A test programming language
that allows migration of test programs between ATE produced by
different manufacturers.
(SM*)
- STANDARIZED TEST METHODOLOGIES
-
Techniques for testing ICs that have been agreed upon by the IC manufacturers.
(SM*)
- STANDARIZED TESTER METRICS
-
Standardized Tester Metrics: Techniques for measuring
test system performance via specifications that have been agreed upon
by test system manufacturers and users.
(SM*)
- STATIC CURRENT TEST (IDDG)
-
Quiescent power supply
current. A test that measures power supply leakage current in a CMOS IC
to determine whether excess current flows, implying a fault.
(SM*)
IDDq testing: a parametric technique to monitor the current, IDD, a
circuit draws when it is in a quiescent state. It is used to detect faults
which increase the normally low IDD.
(SERRA)
- STATISCTICAL PROCESS CONTROL (SPC)
-
The use of statistical methods to analyze a process or its outputs in order to
take appropriate actions to achieve and maintain a state of statistical
control and continuously to improve to process capability.[6]
(SM*)
- STUCK-AT-FAULT
-
A fault in a manufactured circuit
causing an electrical node to be stuck at a logical value of 1 or a
logic value of 0 independent of the input to the circuit. (SM*)
stuck-at fault: a fault model represented by a signal stuck at a fixed logic value (0 or 1).
(SER*)
- SURFACE IMAGING
-
Multilayer resists where the image to
be transferred is focused onto a thin resist layer on the surface when
developed. This thin layer serves as a mask to pattern a thick resist
layer that is employed for forming the image on the wafer.
(SM*)
- SYNTHESIS DESIGN/SYNTHESIS
-
The automatic or semi-automatic creation or refinement of a design at a given level of
abstraction, e.g., local synthesis, layout synthesis, etc.
(SM*)
- SYNTHESIS FOR TESTABILITY
-
The synthesis of logic from
a higher level description incorporating considerations to ensure that
the final design can readily be tested.
(SM*)
- SIGNAL ASSIGNMENT INFORMATION
-
Data added to a design GOOD by FIZZ2GOOD.
Identifies the package pin to which each design port is to be connected.
CHIPS/PRELUDE uses this information with package and base-array information to
determine I/O slots for peripheral macros.
(TI*)
- SIGNATURE ANALYSIS
-
A test where the responses of a device over time is
compacted into a characteristic value called a signature, which is then
compared to a known good one.
(SER*)
- SIMGEN
-
A simulation stimulus formatter program. Translates an MCF input file
into simulator-specific control and stimulus, formatted to generate a
TDLGEN-compatible simulation output. Supports Verilog, Mentor 8 QuickSim II,
LeapFrog, VHDL System Simulator (VSS), and IKOS.
(TI*)
- SCALING LAWS
-
The set of rules describing how
dimension-reduction in ICs interrelate to each other and to the
electrical behavior of the resulting devices. Scaling laws are used to
predict the impacts of size reduction on minimum power supply voltage
and on device speed and power, as well as on the geometry of the structures.
(SM*)
- SCAN (PATH)
-
A linkage of registers in an IC with
associated control mechanisms that enables the registers to be operated
as a shift register in addition to their normal mode of operation. This
permits the registers to be controlled and observed during test mode,
greatly enhancing testability.
(SM*)
- SHORT FLOW
-
A sequence of processing steps in a
semiconductor fabrication facility that is a subset of the steps
required to produce an IC product. A short flow processing sequence is
usually an experiment to evaluate the performance of new or modified
processes or equipments.
(SM*)
- SHORT WIRE PITCH
-
The sum of conductor width and spacing
between conductors for the short conductors on the first interconnect
layer for transistor structures comprising subunits of the IC design.
(SM*)
- SHOW STOPPER
-
A technical problem which, if not resolved, prevents further progress.
(SM*)
- SIGNAL INTEGRITY
-
A condition in which signals can
properly be resolved at their intended level in the presence of noise,
interference, or crosstalk.
(SM*)
- SILICON PROBES
-
Electrical probes on an IC testing
system that have been etched monolithically from a silicon wafer using
a variation of IC processing technology.
(SM*)
- SLASH SHEET
-
A MIL-M-38510 detailed device specification giving the specific
screening and electrical test requirements for a device or family of
related devices. In a MIL-M-38510 part number, the first three digits after
the slash indicate the slash sheet number.
(TI*)
- SMD (STANDARD MICROCIRCUIT DRAWING)
-
See DSCC STANDARD MICROCIRCUIT DRAWING (SMD).
- SINGLE-NET PATH TIMING CONSTRAINT
-
A path timing constraint encompassing only
one gate delay between the driving pin of one gate and the driving pin of the
next gate in the network.
(TI*)
- SOFT MACRO
-
A gate-level netlist description of a logic function supplied by TI
as a standard library part (typically a counter).
(TI*)
- SOLDER-DIP DATE/SOLERABILITY
-
The date of solder dip and/or the date of solderability testing
will be reflected in the manufacturer's certificate of conformance
as the lot date code or the date of lot accept, as applicable.
Solderability testing is defined in MIL-STD-883, Method 2003. (TI*)
(TI*)
- SPECCAP
-
Specification Capture. A graphical user-interface-based tool used
internally to produce a design specification from the design handoff database.
(TI*)
- STANDARD DELAY FORMAT (SDF)
-
An Open Verilog International (OVI) standard file.
(TI*)
- STANDARD LOAD
-
Submicron gate-array standard load = IV110 input capacitance
(approximately equal to 0.04 pF for TGC1000 library). (TI*)
(TI*)
- SUNOS
-
The UNIX operating system supplied on Sun workstations.
(TI*)
- SYNOPSYS
-
Synopsys, Inc. Company specializing in logic synthesis tools.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% TTTTTTTTTTTTTTTTTTTTTTTTTT
- TECHNOLOGY LIBRARIES
-
The codified form of the
information required by computer-aided programs that completely
describes the circuit family being used. These library parameters
include (but are not limited to) items such as delay equations, power
characteristics, geometric shapes, simulation models.
(SM*)
- TESTABILITY
-
The ease with which tests can be generated for and applied to a given circuit.
(SM*)
- TESTABILITY METRICS
-
Measures that determine whether an
IC is easy or hard to test, alternatively, they can measure how
effectively a given set of test vectors tests the IC for a particular
type of fault.
(SM*)
- TEST TECHNIQUES
-
(BIST, ATPG, Iddq, Boundary Scan, etc.):
Any methods used for the expressed purpose of testing ICs.
(SM*)
- TEST STRATEGIES
-
Choosing which techniques from those
available that will be used as part of a specific chip design.
(SM*)
- TEST VECTORS
-
Sequences of signals applied to the pins
of an IC to determine whether the IC is performing as it was designed.
(SM*)
test pattern (test vector): input vector such that the faulty output is
different from the fault-free output (the fault is stimulated and detcted).
SERRA
- TOOL SUITE
-
The set of computer-aided design programs for creating a chip/system.
(SM*)
- TPG
-
See Tester pattern/Program generation.
(SM*)
-
TEST PATTERN / PROGRAM GENERATION (TPG)
-
The generation of a program that runs on an IC hardware tester (IC tester).
The purpose of this program is to permit test vectors to be applied to
the pins of the IC, and measurements made to determine the performance of the IC.
(SM*)
- TIMING
-
The description of the absolute timing of signals propagating through a chip during operation.
(SM*)
- TEST DESCRIPTION LANGUAGE (TDL)
-
A TI-developed test language used as a transfer
format to get your test vectors onto TI testers. TDL format in use is ASIC TDL 91.
(TI*)
- TDL2IKOS
-
A program that converts TDL vectors to IKOS stimulus in a format that
quickly compares actual and expected simulation outputs in IKOS. Also creates
default setup files for IKOS menus.
(TI*)
- TDL2QUICKSIM
-
A program that converts a TDL file to QuickSim II input stimulus
WDB and an expected output WDB. The WDBs compare actual and expected simulation
outputs in QuickSim II.
(TI*)
- TDL2SIMGEN
-
A program that translates/converts a TDL file into a SIMGEN MCF.
(TI*)
- TDL2VERILOG
-
A program that converts a TDL file to Verilog-specific control and
stimulus files (SCF and .vtdl). The SCF compares actual and expected simulation
outputs in Verilog.
(TI*)
- TDLCHKR
-
A rule checking program for production-test TDL files. Checks that TDL
files conform to ASIC TDL 91 standard.
(TI*)
- TDLCMPAR
-
A program that compares two TDL files to determine whether they are
functionally identical. Usually compares minimum and maximum delay simulation
TDL files.
(TI*)
- TDLGEN
-
A program that translates simulator output to TDL. Supports VCD from
Verilog and LeapFrog, Log from Mentor 8 QuickSim II, waveform intermediate
format (WIF) from VHDL System Simulator (VSS), and event stream output (ESO)
and print on change (POC) from IKOS.
(TI*)
- TDLSCRAMBLE
-
A program that merges TI-supplied TDL patterns for compiler cells
into design_level TDL. Generates TDL for ATE and/or simulation.
(TI*)
- TECHNOLOGY FLOW
-
A specific manufacturing line from design, fabrication,
assembly, packaging, and test in a given technology.
(TI*)
- TECHNOLOGY REVIEW BOARD (TRB)
-
Manufacturer's group to review
changes affecting the QM Plan.
(TI*)
- TEMPERATURE
-
A variable defining the operating temperature at which a library is
characterized. Can be varied continuously between the maximum and minimum
characterized values (for example, +125° C and -55° C for TGBx000) by the
user.
(TI*)
- TESTABILITY FEATURE
-
Lets you specify a list of placement rules describing the
connectivity of any logic path you want to group.
(TI*)
- TEST DESCRIPTION LANGUAGE (TDL) RULES
-
Rules you must comply with to hand
off a TDL and a netlist that TI uses to verify your devices in production
(meets the TI ATE requirements).
(TI*)
- THERMAL RESISTANCE
-
Normally stated in terms of C/W, it is the indicator of
the package's ability to dissipate the heat generated by the chip during operation. Theta
JC is the indicator of the chip's ability to pass the heat generated by the semiconductor junctions to
the package, that is the thermal resistance between the semiconductor junction and the case.
(TI*)
- TI
-
Texas Instruments Incorporated.
(TI*)
- TEXAS INSTRUMENTS
DESIGN ENVIRONMENT (TIDE)
-
A shell environment that configures
your design system to use TI tools and libraries. Designed to simplify use of
TI tools in your design system.
(TI*)
- TEST-INTELLIGENT DESIGN SERIES (TiDS)
-
A Cadence testability tool.
(TI*)
- TEXAS INSTRUMENTS DESIGN
SUPPORT SOFTWARE (TIDSS)
-
A generic term used to define
all TI-supplied software.
(TI*)
- TRIPLE LEVEL METAL (TLM)
-
An interconnect technology with three levels of metal.
(TI*)
- TYP
-
Typical. Average timing model. Corresponds to room temperature (25° C),
mean process, and standard supply voltage. Same as nom.
(TI*)
- USER-SPECIFIC ARRAY
-
A custom base array designed for a specific design
application or set of applications. Can support full custom cells, including
memories.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%% VVVVVVVVVVVVVVVVVVVVVVVVVVVV
- VERIFICATION
-
A process by which the correctness of a
design result is confirmed via one or more of the following three
approaches: 1) formal or symbolic analysis of design, 2) simulation of
the design in software form on a host computer, 3) emulation of the
design through implementation in a hardware or combined
software/hardware form.
(SM*)
- VIRTUAL DESIGN
-
An approach to designing a product
whereby the entire process is completed on a computer without the
actual implementation in silicon. Design trade-off and implementation
decisions as well as verification exercises occur entirely with the
help of software tools. Only after all specifications are met and the
designer is satisfied with the result does the actual implementation
take place.
(SM*)
- VIRTUAL FACTORY
-
A rapid prototyping software
environment for factory design and manufacturing engineering based on
computer simulations at various levels, such as process, device,
circuit, equipment, and line.
(SM*)
- WAFER BUMPING
-
The process by which contact points on a
wafer are heightened above the wafer surface by adding conductor
material. These contact bumps are bonded or fused to make all required
electrical connections to tape, packages, or other interconnection
substrates in a single process step. Bumps may be provided on the chip
edges or distributed over the surface of the chip in an area array.
(SM*)
- VALID
-
A company specializing in schematic capture tools.
(TI*)
- VALUE CHANGE DUMP (VCD)
-
A Cadence output format produced by Verilog and LeapFrog
simulators. Used to store information about value changes on
selected signals in the design for later postprocessing.
(TI*)
- VCMP
-
A Cadence Valid-to-Verilog translator.
(TI*)
- VERILOG
-
A Cadence digital simulation tool. Also, a netlist format (Verilog
HDL). Adopted as IEEE standard.
(TI*)
- VERILOG-XL
-
A Verilog simulator from Cadence.
(TI*)
- VERILOG2GOOD
-
A netlist translator program that builds a design GOOD from a
Verilog HDL netlist.
(TI*)
- VERILOG
HARDWARE DESCRIPTION LANGUAGE (HDL)
-
A popular HDL, now defined
as an open standard (Open Verilog). Principally used with the Cadence Verilog
simulator. Supports behavioral, register transfer level (RTL), gate-level
circuit description, and stimulus description in one language.
(TI*)
- VERITIME
-
A Cadence timing analysis tool.
(TI*)
- VHDL
-
VHSIC Hardware Description Language. Developed under guidelines from the
U.S. Department of Defense and adapted as IEEE Standard 1076.
(TI*)
- VHDL2GOOD
-
A netlist translator program that builds a design GOOD from a VHDL
netlist.
(TI*)
- VHSIC
-
Very High Scale Integrated Circuit.
(TI*)
- VOLTAGE
-
A variable defining the operating voltage at which the library is
characterized. You can change this variable continuously between the minimum
and maximum characterized values (for example, 4.50 V and 5.50 V for TGC1000).
(TI*)
- VSS
-
VHDL System Simulator. A Synopsys tool suite that provides VHSIC Hardware
Description Language (VHDL) simulation and circuit debugging.
(TI*)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% WWWWWWWWWWWWWWWWWWWWWWWWWWWW
- WAFER FAB
-
Landing Pad: Contact metal pads on a wafer usually
associated with test probes and existing for test only.
(SM*)
- WAVEFORM DATABASE (WDB)
-
Mentor binary format used and produced by QuickSim II.
(TI*)
- WAFER FAB
-
The wafer manufacturing facility of the semiconductor manufacturing process.
(TI*)
- WAVEFORM INTERMEDIATE FORMAT (WIF)
-
A Synopsys output format produced by the VHDL
System Simulator (VSS).
(TI*)
- WAFER SORT
-
The process after wafer fabrication during
which the electrical parameters of integrated circuits are tested for
functionality. Probes contact the pads of the circuit to conduct the
test.[5]
(SM*)