library IEEE;

use IEEE.std_logic_1164.all;

package CONV_PACK_tap_control is

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_tap_control;

library IEEE;

use IEEE.std_logic_1164.all;

use work.CONV_PACK_tap_control.all;

entity tap_control is

   port( trst, tms, tck : in std_logic;  reset, enable, select_1, clk_ir, sfir,
         udir, clk_dr, sfdr, uddr : out std_logic);

end tap_control;

architecture SYN_arch1 of tap_control is

   component CND2IX1
      port( Z : out std_logic;  A, B : in std_logic);
   end component;
   
   component CIVX2
      port( Z : out std_logic;  A : in std_logic);
   end component;
   
   component CNR2IX1
      port( Z : out std_logic;  A, B : in std_logic);
   end component;
   
   component CANR11X1
      port( Z : out std_logic;  A, B, C, D : in std_logic);
   end component;
   
   component COND11X1
      port( Z : out std_logic;  A, B, C, D : in std_logic);
   end component;
   
   component CFD1QXL
      port( Q : out std_logic;  D, CP : in std_logic);
   end component;
   
   component CLDP1QXL
      port( Q : out std_logic;  D, G : in std_logic);
   end component;
   
   component CNR3XL
      port( Z : out std_logic;  A, B, C : in std_logic);
   end component;
   
   component CANR1XL
      port( Z : out std_logic;  A, B, C : in std_logic);
   end component;
   
   component CLDP1XL
      port( Q, QN : out std_logic;  D, G : in std_logic);
   end component;
   
   component COR4X1
      port( Z : out std_logic;  A, B, C, D : in std_logic);
   end component;
   
   component CAOR2X1
      port( Z : out std_logic;  A, B, C, D : in std_logic);
   end component;
   
   component COAN1X1
      port( Z : out std_logic;  A, B, C : in std_logic);
   end component;
   
   component CAN4X1
      port( Z : out std_logic;  A, B, C, D : in std_logic);
   end component;
   
   component CAOR1X1
      port( Z : out std_logic;  A, B, C : in std_logic);
   end component;
   
   component CMXI2X1
      port( Z : out std_logic;  A0, A1, S : in std_logic);
   end component;
   
   component COR3X1
      port( Z : out std_logic;  A, B, C : in std_logic);
   end component;
   
   signal present_state_2_port, n_1504, n_1601, n_1486, present_state_0_port, 
      next_state_1_port, n_1462, next_state_3_port, n_1492, next_state_2_port, 
      next_state_0_port, present_state_1_port, n_1468, present_state_3_port, 
      n_1583, n_1474, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, 
      n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
      n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, 
      n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, 
      n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, 
      n140, n141, n142, n143, n144 : std_logic;

begin
   
   U56 : CND2IX1 port map( Z => n120, A => n115, B => n117);
   U57 : CND2IX1 port map( Z => n118, A => n120, B => n119);
   U58 : CIVX2 port map( Z => n121, A => tms);
   U59 : CND2IX1 port map( Z => n111, A => n112, B => present_state_2_port);
   U60 : CND2IX1 port map( Z => n117, A => n109, B => present_state_3_port);
   U61 : CNR2IX1 port map( Z => n_1601, A => n_1504, B => trst);
   U62 : CNR2IX1 port map( Z => n_1583, A => n_1486, B => trst);
   U63 : CANR11X1 port map( Z => next_state_1_port, A => n95, B => n96, C => 
                           n97, D => n98);
   U64 : COND11X1 port map( Z => n123, A => tms, B => n108, C => n110, D => 
                           n124);
   U65 : CND2IX1 port map( Z => n96, A => n131, B => n113);
   U66 : CANR11X1 port map( Z => next_state_2_port, A => n99, B => n100, C => 
                           n101, D => n98);
   U67 : CIVX2 port map( Z => n98, A => trst);
   U68 : CNR2IX1 port map( Z => next_state_3_port, A => n102, B => trst);
   U69 : CND2IX1 port map( Z => n105, A => n125, B => present_state_1_port);
   U70 : CNR2IX1 port map( Z => n90, A => n108, B => present_state_1_port);
   U71 : CND2IX1 port map( Z => n124, A => n89, B => n113);
   U72 : CND2IX1 port map( Z => n106, A => n129, B => present_state_2_port);
   present_state_reg_0_label : CFD1QXL port map( Q => present_state_0_port, D 
                           => next_state_0_port, CP => tck);
   present_state_reg_1_label : CFD1QXL port map( Q => present_state_1_port, D 
                           => next_state_1_port, CP => tck);
   present_state_reg_2_label : CFD1QXL port map( Q => present_state_2_port, D 
                           => next_state_2_port, CP => tck);
   present_state_reg_3_label : CFD1QXL port map( Q => present_state_3_port, D 
                           => next_state_3_port, CP => tck);
   sfdr_reg : CLDP1QXL port map( Q => sfdr, D => n_1504, G => trst);
   udir_reg : CLDP1QXL port map( Q => udir, D => n_1492, G => trst);
   sfir_reg : CLDP1QXL port map( Q => sfir, D => n_1486, G => trst);
   select_1_reg : CLDP1QXL port map( Q => select_1, D => n_1474, G => trst);
   enable_reg : CLDP1QXL port map( Q => enable, D => n_1468, G => trst);
   reset_reg : CLDP1QXL port map( Q => reset, D => n_1462, G => trst);
   U73 : CNR3XL port map( Z => n79, A => present_state_1_port, B => n110, C => 
                           n113);
   U74 : CANR1XL port map( Z => n80, A => n89, B => n125, C => n_1486);
   n81 <= '1';
   n82 <= '1';
   n83 <= '0';
   U78 : CIVX2 port map( Z => n129, A => n117);
   U79 : CIVX2 port map( Z => n89, A => n84);
   U80 : CIVX2 port map( Z => n_1504, A => n137);
   U81 : CND2IX1 port map( Z => n137, A => n129, B => n113);
   U82 : CIVX2 port map( Z => n_1486, A => n85);
   U83 : CND2IX1 port map( Z => n85, A => n89, B => n108);
   U84 : CND2IX1 port map( Z => n113, A => present_state_2_port, B => 
                           present_state_0_port);
   U85 : CND2IX1 port map( Z => n108, A => present_state_0_port, B => 
                           present_state_2_port);
   U86 : CND2IX1 port map( Z => n84, A => present_state_3_port, B => n109);
   U87 : CIVX2 port map( Z => n109, A => present_state_1_port);
   uddr_reg : CLDP1XL port map( Q => uddr, QN => n142, D => n83, G => trst);
   clk_ir_reg : CLDP1XL port map( Q => clk_ir, QN => n143, D => n82, G => 
                           n_1583);
   clk_dr_reg : CLDP1XL port map( Q => clk_dr, QN => n144, D => n81, G => 
                           n_1601);
   U88 : CND2IX1 port map( Z => n_1462, A => n86, B => present_state_0_port);
   U89 : COR4X1 port map( Z => n_1468, A => n_1504, B => n87, C => n88, D => 
                           n_1486);
   U90 : COR4X1 port map( Z => n_1474, A => n89, B => n90, C => n86, D => n91);
   U91 : CAOR2X1 port map( Z => n_1492, A => n92, B => present_state_3_port, C 
                           => n91, D => present_state_1_port);
   U92 : COAN1X1 port map( Z => next_state_0_port, A => n93, B => n94, C => 
                           trst);
   U93 : CAN4X1 port map( Z => n102, A => n80, B => n95, C => n100, D => n103);
   U94 : CAN4X1 port map( Z => n104, A => n105, B => n106, C => n107, D => n80)
                           ;
   U95 : CIVX2 port map( Z => n110, A => present_state_3_port);
   U96 : CIVX2 port map( Z => n112, A => present_state_0_port);
   U97 : CND2IX1 port map( Z => n114, A => present_state_2_port, B => n112);
   U98 : CND2IX1 port map( Z => n107, A => n115, B => n110);
   U99 : CND2IX1 port map( Z => n116, A => present_state_1_port, B => 
                           present_state_3_port);
   U100 : CAOR1X1 port map( Z => n122, A => n91, B => n109, C => n79);
   U101 : CND2IX1 port map( Z => n126, A => n128, B => n127);
   U102 : CAOR1X1 port map( Z => n130, A => n131, B => present_state_0_port, C 
                           => n132);
   U103 : CND2IX1 port map( Z => n133, A => n80, B => n88);
   U104 : CND2IX1 port map( Z => n134, A => n80, B => n118);
   U105 : CND2IX1 port map( Z => n135, A => n136, B => n122);
   U106 : CMXI2X1 port map( Z => n93, A0 => n104, A1 => n99, S => tms);
   U107 : COAN1X1 port map( Z => n128, A => n108, B => n116, C => n137);
   U108 : COAN1X1 port map( Z => n136, A => n112, B => n106, C => n138);
   U109 : COR3X1 port map( Z => n94, A => n119, B => n79, C => n88);
   U110 : CND2IX1 port map( Z => n139, A => n125, B => n116);
   U111 : CIVX2 port map( Z => n119, A => n139);
   U112 : CIVX2 port map( Z => n132, A => n120);
   U113 : CIVX2 port map( Z => n127, A => n96);
   U114 : CIVX2 port map( Z => n88, A => n124);
   U115 : CND2IX1 port map( Z => n140, A => n115, B => n116);
   U116 : CIVX2 port map( Z => n87, A => n140);
   U117 : CIVX2 port map( Z => n86, A => n106);
   U118 : CIVX2 port map( Z => n92, A => n105);
   U119 : CIVX2 port map( Z => n91, A => n107);
   U120 : CIVX2 port map( Z => n131, A => n116);
   U121 : CIVX2 port map( Z => n115, A => n114);
   U122 : CIVX2 port map( Z => n125, A => n111);
   U123 : CIVX2 port map( Z => n95, A => n123);
   U124 : CIVX2 port map( Z => n100, A => n122);
   U125 : CIVX2 port map( Z => n141, A => n118);
   U126 : CAOR1X1 port map( Z => n103, A => n141, B => n140, C => n121);
   U127 : CIVX2 port map( Z => n99, A => n126);
   U128 : CIVX2 port map( Z => n138, A => n_1492);
   U129 : CMXI2X1 port map( Z => n101, A0 => n130, A1 => n133, S => tms);
   U130 : CMXI2X1 port map( Z => n97, A0 => n134, A1 => n135, S => tms);

end SYN_arch1;