LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top is port ( Rst_n : in std_logic; Clock : in std_logic; Start : in std_logic; InputData : in unsigned(7 downto 0); result : out unsigned(5 downto 0) ); end top; architecture behav OF top IS component FSM port ( Rst_n : in std_logic; Clock : in std_logic; IsZero : in std_logic; Smaller : in std_logic; Start : in std_logic; Ready : in std_logic; LdIntReg : out std_logic; SelAdder : out std_logic; LdResultReg : out std_logic; ShiftData : out std_logic; LdIO : out std_logic; SelOne : out std_logic; Concat1 : out std_logic; LdSub : out std_logic; IncrCnt : out std_logic ); end component; component ComputeUnit port ( Rst_n : in std_logic; Clock : in std_logic; LdIntReg : in std_logic; SelAdder : in std_logic; LdResultReg : in std_logic; ShiftData : in std_logic; LdIO : in std_logic; SelOne : in std_logic; Concat1 : in std_logic; LdSub : in std_logic; InputData : in unsigned(7 downto 0); IsZero : out std_logic; Smaller : out std_logic; result : out unsigned(5 downto 0) ); end component; component counter port ( IncrCnt : in std_logic; Rst_n : in std_logic; Clock : in std_logic; Ready : out std_logic ); end component; signal IsZero, Smaller, Ready, LdIntReg, LdResultReg, ShiftData : std_logic; signal SelAdder, LdIO, SelOne, Concat1, IncrCnt, LdSub : std_logic; BEGIN -- behav FSMuut : FSM port map ( Rst_n => Rst_n, Clock => Clock, IsZero => IsZero, Smaller => Smaller, Start => Start, Ready => Ready, LdIntReg => LdIntReg, SelAdder => SelAdder, LdResultReg => LdResultReg, ShiftData => ShiftData, LdIO => LdIO, SelOne => SelOne, Concat1 => Concat1, LdSub => LdSub, IncrCnt => IncrCnt ); ComputeUnitUUT : ComputeUnit port map ( Rst_n => Rst_n, Clock => Clock, LdIntReg => LdIntReg, SelAdder => SelAdder, LdResultReg => LdResultReg, ShiftData => ShiftData, LdIO => LdIO, SelOne => SelOne, Concat1 => Concat1, LdSub => LdSub, InputData => InputData, IsZero => IsZero, Smaller => Smaller, result => result ); counterUUT : counter port map ( IncrCnt => IncrCnt, Rst_n => Rst_n, Clock => Clock, Ready => Ready ); END behav;