LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity IntReg is port ( LdIntReg : in std_logic; SelAdder : in std_logic; Rst_n : in std_logic; Clock : in std_logic; Data : in unsigned (1 downto 0); Adder : in unsigned (5 downto 0); IntRegOut : out unsigned(7 downto 0) ); end IntReg; architecture behav OF IntReg IS signal l_data : unsigned(7 downto 0); signal upper : unsigned(5 downto 0); BEGIN -- behav mux : process(Adder, l_data, SelAdder) begin if SelAdder = '1' then upper <= Adder; else upper <= l_data(5 downto 0); end if; end process; Myregister : process (Rst_n, Clock, LdIntReg) begin if Rst_n = '0' then l_data <= (others => '0'); elsif falling_edge(Clock) then if LdIntReg = '1' then l_data(7 downto 2) <= upper; l_data(1 downto 0) <= Data; end if; end if; end process; IntRegOut <= l_data; END behav;